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TL072Dual FET-input operational amplifier

Two high-impedance analog channels in one compact IC.

Manufacturer-referenced

Texas Instruments · TL072CP

PDIP-8SLOS080W · July 2025

TL072 integrates two FET-input operational amplifiers. Each channel compares a pair of input voltages and uses external negative feedback to control its gain. The physical example uses channel A as a gain-of-three amplifier and channel B as a voltage follower. A shared 0.50 V input gives ideal outputs of 1.50 V and 0.50 V from a ±15 V supply. This page follows TI’s July 2025 reference for the C-grade P and D packages. Its revised P/D specifications differ from the legacy PS package; the manufacturer’s package-specific columns are kept separate.

Real View

TL072CP black package with silver leads and readable markings.
TL072CP · PDIP-8Package illustration

Pinout

TL072CPPDIP-8Top view
Select a pin to see its functionPDIP-8 · 8 pins

PCB Footprint

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3D View

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Analog outputsAnalog inputsShared supply rails
TL072CPPDIP-8Top view

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1
PIN 1 · Analog outputs

OUT1

Analog output

Function

Channel A output.

How to connect

Return to IN1− through 20 kΩ; connect a high-impedance meter.

At a glance

Dual FET-input operational amplifier

High input impedance suits voltage buffering and active filters. Each channel needs its own negative-feedback path.

4.5–40 V · TI P/D packages, Rev WSupply span
5.25 MHz · P/D packagesTypical bandwidth
0–70 °CC-grade ambient
20 V/µs · specified testTypical slew rate

Operating profile

TL072CP

Selected package
PDIP-8TL072CP
Independent channels
2Separate feedback; shared rails
Example outputs
1.50 / 0.50V · ideal A / B

Operating conditions

Key parameters and their test conditions

Total supply span
4.5–40 VConditions / notes: V+ minus V−; Rev W, all except NS/PS/M
Ambient temperature
0 to +70°CConditions / notes: TL072C grade
Recommended input range
V− + 4 V to V+ + 0.1 VConditions / notes: Observe supply and signal restrictions
Example supply
+15 V / −15 VConditions / notes: 0 V is the midpoint
Legacy PS package
10–30 V total supplyConditions / notes: Different column; not the package illustrated here

Package details

Follows the selected physical package

Manufacturer
Texas Instruments
Part number
TL072CP
Package
PDIP-8
Connections
8 pins
Mounting
Through-hole
Lead pitch
2.54 mm
Package code
dip
Thermal reference
Board and package dependent; see manufacturer data

Connections by function

Select a pin to open its function, electrical notes and wiring guidance.

Analog outputs2 pins

Analog inputs4 pins

Shared supply rails2 pins

Values apply to the stated grade and conditions. Absolute maximum ratings are stress limits.SLOS080W · July 2025

Compare each input pair

The FET input stage draws very little bias current at room temperature. Source resistance, board leakage and temperature still affect the input error.

Set two different gains

Channel A uses 20 kΩ feedback and 10 kΩ to the 0 V midpoint, giving a gain of three. Channel B directly feeds its output back to its negative input, giving unity gain.

Check headroom and speed

With a 0.50 V input, the ideal outputs are 1.50 V and 0.50 V. Real output also depends on input offset, resistor accuracy, loading, noise and signal frequency.

Both channels share the supply rails but have independent feedback paths. The diagram shows a low-frequency, light-load example; use the specified limits for your actual circuit.

Two FET-input amplifier channels inside a compact TL072 IC. A: positive 3, negative 2, output 1. B: positive 5, negative 6, output 7. Shared supplies 8 and 4.
Functional cutaway; internal compensation is included. External feedback sets the gain.
TL072CP on ±15 V rails. VIN 0.50 V connects to pins 3 and 5. Pin 1 feeds pin 2 through 20 kΩ; 10 kΩ joins pin 2 to 0 V. Pin 7 joins pin 6 directly. Both supply rails have 100 nF bypass to 0 V.
All VIN labels share one signal. All ground symbols are the 0 V supply midpoint.

Pin reference

Select a pin to explore its function and connection.

8 pins
PinSignalTypeFunction
OUT1Analog outputChannel A output.
IN1−Inverting inputChannel A negative-feedback node.
IN1+Non-inverting inputChannel A signal input.
V−Negative supplyNegative rail shared by both amplifiers.
IN2+Non-inverting inputChannel B signal input.
IN2−Inverting inputChannel B feedback input.
OUT2Analog outputChannel B output.
V+Positive supplyPositive rail shared by both amplifiers.
PDIP-8 · Top view · Select a pin number to inspect its connection.

Operating conditions

TI TL072C · P/D package columns

ParameterValueConditions / notes
Total supply span4.5–40 VV+ minus V−; Rev W, all except NS/PS/M
Ambient temperature0 to +70°CTL072C grade
Recommended input rangeV− + 4 V to V+ + 0.1 VObserve supply and signal restrictions
Example supply+15 V / −15 V0 V is the midpoint
Legacy PS package10–30 V total supplyDifferent column; not the package illustrated here

Values follow the stated revision and package. Do not apply current P/D limits to an unidentified older die.

DC characteristics

±15 V · 25°C unless stated

ParameterValueConditions / notes
Input offset voltage3 mV typical; 10 mV maximumTL072C; RS = 50 Ω
Input offset, full temperature13 mV maximum0–70°C
Input bias current65 pA typical; 200 pA maximum7 nA maximum over temperature
Input offset current5 pA typical; 100 pA maximum10 nA maximum over temperature
Supply current per amplifier1.4 mA typical; 2.5 mA maximumNo load; output at 0 V
Common-mode range±11 V minimum; −12 to +15 V typical±15 V test supply
Output swing±12 V minimum; ±13.5 V typicalRL = 10 kΩ

Typical values describe representative devices; use specified limits for error budgets.

Dynamic characteristics

TI Rev W · P/D packages

ParameterValueConditions / notes
Gain-bandwidth product5.25 MHz typicalP/D package column
Slew rate8 V/µs minimum; 20 V/µs typical10 V input; CL = 100 pF; RL = 2 kΩ
Input voltage noise at 1 kHz37 nV/√Hz typicalAll except PS/NS/M
Input voltage noise at 10 kHz21 nV/√Hz typicalP/D package column
Phase margin56° typicalGain +1; RL = 10 kΩ; CL = 20 pF

Bandwidth, slew rate and settling behavior are different limits; check all three for a changing signal.

Two-channel amplifier example

±15 V rails · 0 V signal reference

ParameterValueConditions / notes
Input VIN0.50 VPins 3 and 5; common signal ground
Channel A feedback20 kΩOUT1 pin 1 to IN1− pin 2
Channel A ground resistor10 kΩIN1− pin 2 to 0 V
Channel A ideal output1.50 V0.50 × (1 + 20 / 10)
Channel B feedbackDirect connectionOUT2 pin 7 to IN2− pin 6
Channel B ideal output0.50 VUnity-gain follower
Bypass capacitors100 nF per railEach supply rail to the 0 V midpoint

The 0 V reference is not the negative supply pin. Keep both rail-bypass loops short.

Physical pin reference

TL072CP · PDIP-8

ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
Channel AOUT1 1; IN1− 2; IN1+ 3Independent feedback loop
Channel BIN2+ 5; IN2− 6; OUT2 7Independent feedback loop
SupplyV− 4; V+ 8Shared by both channels
Package orientationTop view; pin 1 at the markerCounterclockwise numbering

This dual-amplifier pinout differs from single amplifiers such as TL081 or LM741.

Take it into ProTech

Find TL072 in the Components Library to place its schematic symbol and connect its pins.

Reference page · circuit simulation model not yet availableOpen ProTech

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