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Quad FET-input operational amplifier

TL074 Specifications

Review TL074 electrical specifications, operating conditions and package details.

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Key specifications

Keep every amplifier input defined. The illustrated followers close their own feedback loops; none of the spare channels is left floating.

Independent amplifiers4 Shared power rails
Example rails±15 V · 0 V signal midpoint
C-grade ambient0–70 °C
Original-table input bias65 pA typical · 25°C

Operating profile

Supply, signals and operating conditions

TL074 operating profile
ParameterValueConditions / notes
Selected packagePDIP-14TL074CN
Channel A ideal gain4×30 kΩ feedback / 10 kΩ to midpoint
Check shipment CSOSFAB / RFBManufacturer tables differ by die flow
Use these values with the stated grade and test conditions.

Package details

TL074CN · PDIP-14

Selected package
Selected TL074 physical package
PropertyDetails
ManufacturerTexas Instruments
Part numberTL074CN
PackagePDIP-14
Connections14 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codedip
Thermal referenceBoard and package dependent; see manufacturer data

Package, grade and silicon selection

TI revision W · manufacturer ordering data

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ParameterValueConditions / notes
Through-hole orderTL074CNPDIP-14 N; commercial 0–70°C
SMD orderTL074CDRSOIC-14 D; commercial 0–70°C
Legacy flowCSO SFABUse sections 5.8, 5.9 and 5.11
Latest flowCSO RFBUse sections 5.7 and 5.10
Non-H, non-M ordersMay use either flowConfirm shipment identity; suffix alone is insufficient
Page electrical referenceOriginal-die tables 5.8 and 5.9No TL074H accuracy or temperature claims substituted

Use the manufacturer PDF and shipment label together.

Supply and signal conditions

Selected N/D package; original-table characterization

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ParameterValueConditions / notes
Illustrated split rails+15 V and −15 V30 V total supply span
Revision-W recommended span4.5–40 V for the all-other-devices categoryNS/PS and M exceptions: 10–30 V; verify die-specific applicability
Revision-W recommended inputVCC−+4 V to VCC++0.1 VAll-other-devices category; do not treat as rail-to-rail output
C-grade ambient0 to70°CNot I, M or H temperature limits
Common-mode at ±15 V±11 V minimum; −12 to+15 V typicalOriginal-die electrical table
Output swing, RL10 kΩ±12 V minimum; ±13.5 V typicalAt ±15 V; ±12 V minimum over temperature
Output swing, RL≥2 kΩ±10 V minimumOutput loading reduces swing

The ±15 V example has generous input and output headroom.

Original-die DC characteristics

C-grade · ±15 V ·25°C unless stated

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ParameterValueConditions / notes
Input offset voltage3 mV typical; 10 mV maximum13 mV maximum over full temperature; RS50 Ω
Input offset drift±18 µV/°C typicalFull-temperature characterization
Input bias current65 pA typical; 200 pA maximum7 nA maximum over full temperature
Input offset current5 pA typical; 100 pA maximum10 nA maximum over full temperature for C grade
Quiescent current per amplifier1.4 mA typical; 2.5 mA maximumNo load; VO0 V; four channels total 5.6 mA typ.
Open-loop gain25 V/mV minimum; 200 V/mV typicalC grade; 15 V/mV minimum over full temperature
CMRR / PSRR70 dB minimum; 100 dB typicalC grade; source test conditions retained

Low room-temperature bias current does not imply negligible high-temperature leakage.

Original-die AC characteristics

Revision-W tables; N/D package category

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ParameterValueConditions / notes
Gain-bandwidth product5.25 MHz typicalAll-other-devices category; NS/PS/M table entry is 3 MHz
Slew rate8 V/µs minimum; 20 V/µs typicalVI10 V, CL100 pF, RL2 kΩ; C grade
Input voltage noise at1 kHz37 nV/√Hz typicalAll-other-devices category
Input voltage noise at10 kHz21 nV/√Hz typicalNoise density, not integrated RMS noise
Low-frequency voltage noise1.4 µV RMS typical0.1–10 Hz; all-other-devices category
Input current noise10 fA/√Hz typical1 kHz; RS20 Ω
Phase margin56° typicalGain+1, RL10 kΩ, CL20 pF

These revision-W values must not be silently replaced by older family summaries or the H-die table.

Gain four and three followers

Split-supply circuit with defined unused channels

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ParameterValueConditions / notes
Input VIN0.40 VTo pins3,5,10,12; referenced to0 V
A feedback30 kΩ fromOUT1 toIN−210 kΩ fromIN−2 to0 V
A ideal output1.60 V0.40×(1+30/10)
B followerOUT7 connected toIN−6Input5; ideal output0.40 V
C followerOUT8 connected toIN−9Input10; ideal output0.40 V
D followerOUT14 connected toIN−13Input12; ideal output0.40 V
Bypass100 nF per supply rail to0 VPositive pin4; negative pin11

The midpoint is not pin11. Both supplies are required for the shown circuit.

Physical pin and layout reference

TL074CN · PDIP-14

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ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
ChannelA3 IN+;2 IN−;1 OUTIndependent amplifier
ChannelB5 IN+;6 IN−;7 OUTIndependent amplifier
ChannelC10 IN+;9 IN−;8 OUTIndependent amplifier
ChannelD12 IN+;13 IN−;14 OUTIndependent amplifier
Shared rails4 VCC+;11 VCC−Top-view counterclockwise numbering
PCB practiceShort feedback and bypass loopsKeep output currents away from sensitive input returns

Check the exact package before manufacture.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Analog outputs4 pins

Analog inputs8 pins

Supply2 pins

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

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