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Quad FET-input operational amplifier

TL074 Reference Tables

Search the TL074 pin reference and manufacturer-referenced specification tables.

Package view
Selected packagePDIP-14TL074CN
Physical connections14 pinsPackage-specific numbering
Reference collection7 tables41 parameters & pin functions

Pin reference

Signal names, electrical functions and connection guidance

PDIP-14
Physical pin numbers14 pins

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TL074 pin functions and connections
PinSignalTypeFunction & connection
OUTAAnalog outputChannel A output.
Connection guidance

Connect the 30 kΩ feedback resistor and high-impedance meter.

Output swing requires supply headroom.

INA−Inverting inputChannel A negative-feedback node.
Connection guidance

Join 30 kΩ from OUTA and 10 kΩ to the 0 V midpoint.

INA+Non-inverting inputChannel A positive input.
Connection guidance

Connect to the common 0.40 V input in the example.

Stay within the specified input common-mode range.

VCC+Positive supplyPositive rail shared by four channels.
Connection guidance

Connect +15 V; bypass locally to 0 V with 100 nF.

INB+Non-inverting inputChannel B positive input.
Connection guidance

Connect to the common 0.40 V input in the example.

Stay within the specified input common-mode range.

INB−Inverting inputChannel B negative-feedback node.
Connection guidance

Join directly to OUTB for a follower.

OUTBAnalog outputChannel B output.
Connection guidance

Connect to its own negative input; no external load in this example.

Output swing requires supply headroom.

OUTCAnalog outputChannel C output.
Connection guidance

Connect to its own negative input; no external load in this example.

Output swing requires supply headroom.

INC−Inverting inputChannel C negative-feedback node.
Connection guidance

Join directly to OUTC for a follower.

INC+Non-inverting inputChannel C positive input.
Connection guidance

Connect to the common 0.40 V input in the example.

Stay within the specified input common-mode range.

VCC−Negative supplyNegative rail shared by four channels.
Connection guidance

Connect −15 V; bypass locally to 0 V with 100 nF.

This is not signal ground in the split-supply example.

IND+Non-inverting inputChannel D positive input.
Connection guidance

Connect to the common 0.40 V input in the example.

Stay within the specified input common-mode range.

IND−Inverting inputChannel D negative-feedback node.
Connection guidance

Join directly to OUTD for a follower.

OUTDAnalog outputChannel D output.
Connection guidance

Connect to its own negative input; no external load in this example.

Output swing requires supply headroom.

PDIP-14 · Top view · Select a pin number to open its interactive pinout.

Package, grade and silicon selection

TI revision W · manufacturer ordering data

Manufacturer-referenced values6 parameters

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ParameterValueConditions / notes
Through-hole orderTL074CNPDIP-14 N; commercial 0–70°C
SMD orderTL074CDRSOIC-14 D; commercial 0–70°C
Legacy flowCSO SFABUse sections 5.8, 5.9 and 5.11
Latest flowCSO RFBUse sections 5.7 and 5.10
Non-H, non-M ordersMay use either flowConfirm shipment identity; suffix alone is insufficient
Page electrical referenceOriginal-die tables 5.8 and 5.9No TL074H accuracy or temperature claims substituted

Use the manufacturer PDF and shipment label together.

Supply and signal conditions

Selected N/D package; original-table characterization

Manufacturer-referenced values7 parameters

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ParameterValueConditions / notes
Illustrated split rails+15 V and −15 V30 V total supply span
Revision-W recommended span4.5–40 V for the all-other-devices categoryNS/PS and M exceptions: 10–30 V; verify die-specific applicability
Revision-W recommended inputVCC−+4 V to VCC++0.1 VAll-other-devices category; do not treat as rail-to-rail output
C-grade ambient0 to70°CNot I, M or H temperature limits
Common-mode at ±15 V±11 V minimum; −12 to+15 V typicalOriginal-die electrical table
Output swing, RL10 kΩ±12 V minimum; ±13.5 V typicalAt ±15 V; ±12 V minimum over temperature
Output swing, RL≥2 kΩ±10 V minimumOutput loading reduces swing

The ±15 V example has generous input and output headroom.

Original-die DC characteristics

C-grade · ±15 V ·25°C unless stated

Manufacturer-referenced values7 parameters

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ParameterValueConditions / notes
Input offset voltage3 mV typical; 10 mV maximum13 mV maximum over full temperature; RS50 Ω
Input offset drift±18 µV/°C typicalFull-temperature characterization
Input bias current65 pA typical; 200 pA maximum7 nA maximum over full temperature
Input offset current5 pA typical; 100 pA maximum10 nA maximum over full temperature for C grade
Quiescent current per amplifier1.4 mA typical; 2.5 mA maximumNo load; VO0 V; four channels total 5.6 mA typ.
Open-loop gain25 V/mV minimum; 200 V/mV typicalC grade; 15 V/mV minimum over full temperature
CMRR / PSRR70 dB minimum; 100 dB typicalC grade; source test conditions retained

Low room-temperature bias current does not imply negligible high-temperature leakage.

Original-die AC characteristics

Revision-W tables; N/D package category

Manufacturer-referenced values7 parameters

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ParameterValueConditions / notes
Gain-bandwidth product5.25 MHz typicalAll-other-devices category; NS/PS/M table entry is 3 MHz
Slew rate8 V/µs minimum; 20 V/µs typicalVI10 V, CL100 pF, RL2 kΩ; C grade
Input voltage noise at1 kHz37 nV/√Hz typicalAll-other-devices category
Input voltage noise at10 kHz21 nV/√Hz typicalNoise density, not integrated RMS noise
Low-frequency voltage noise1.4 µV RMS typical0.1–10 Hz; all-other-devices category
Input current noise10 fA/√Hz typical1 kHz; RS20 Ω
Phase margin56° typicalGain+1, RL10 kΩ, CL20 pF

These revision-W values must not be silently replaced by older family summaries or the H-die table.

Gain four and three followers

Split-supply circuit with defined unused channels

Manufacturer-referenced values7 parameters

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ParameterValueConditions / notes
Input VIN0.40 VTo pins3,5,10,12; referenced to0 V
A feedback30 kΩ fromOUT1 toIN−210 kΩ fromIN−2 to0 V
A ideal output1.60 V0.40×(1+30/10)
B followerOUT7 connected toIN−6Input5; ideal output0.40 V
C followerOUT8 connected toIN−9Input10; ideal output0.40 V
D followerOUT14 connected toIN−13Input12; ideal output0.40 V
Bypass100 nF per supply rail to0 VPositive pin4; negative pin11

The midpoint is not pin11. Both supplies are required for the shown circuit.

Physical pin and layout reference

TL074CN · PDIP-14

Manufacturer-referenced values7 parameters

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ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
ChannelA3 IN+;2 IN−;1 OUTIndependent amplifier
ChannelB5 IN+;6 IN−;7 OUTIndependent amplifier
ChannelC10 IN+;9 IN−;8 OUTIndependent amplifier
ChannelD12 IN+;13 IN−;14 OUTIndependent amplifier
Shared rails4 VCC+;11 VCC−Top-view counterclockwise numbering
PCB practiceShort feedback and bypass loopsKeep output currents away from sensitive input returns

Check the exact package before manufacture.

Read each value with its conditions

Typical values describe the stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Texas Instruments · SLOS080W · July 2025
Official PDF datasheet

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