PCB plane capacitance: why it matters, the formula, cavity resonances, and a worked example
A power plane over a ground plane is a capacitor spread across the whole board, and above a few hundred megahertz, where every discrete capacitor has turned into an inductor, it is the only decoupling left. Its value is small, a few nanofarads for a large board on a thin prepreg, but it comes with almost no inductance. This calculator gives the capacitance from the planes' overlap, the dielectric between them and εr, the fringing at the edges, the impedance at a frequency, the plane pair's cavity resonances and the frequency below which it behaves as a lumped capacitor, and the spacing or area a target would need, with the planes drawn in cross-section and from above.
How to use the plane capacitance calculator
- Type the overlap of the two planes, length and width, and the dielectric thickness between them (the prepreg or core, not the whole board).
- Pick the substrate in the menu row to fill in εr, or type the laminate's figure.
- Add a frequency for the impedance and to see whether the pair is still a lumped capacitor there, or a target capacitance for the spacing it needs. The Spacing table tab compares the common prepreg thicknesses.
Why plane capacitance matters
Every decoupling capacitor has a few hundred picohenries of inductance in its body, pads and vias, so a 100 nF part is useful only up to a few tens of megahertz and becomes an inductor beyond; smaller parts reach higher, but none beyond a few hundred megahertz. The plane pair has no such limit: its capacitance is distributed, its inductance is that of a sheet, and it keeps supplying the fast edge currents that chips draw at gigahertz rates. A thin power–ground spacing is therefore the first decision in a high-speed stack-up, and the reason four-layer boards put the planes on the inner layers close together rather than at the outside.
The formula
C = ε₀ εr A / d ε₀ = 8.854 pF/m
The parallel-plate formula: the overlapping area over the spacing, times the permittivity of free space and the laminate's dielectric constant. On FR-4 it comes to about 38 pF per square centimetre for a 0.1 mm spacing and 380 pF for 0.01 mm. Fringing at the edges adds a share of roughly d/π per unit of perimeter, negligible for planes but a few percent for small patches. Splits, slots and the anti-pads around vias reduce the overlap, and a split plane is two capacitors, not one.
Cavity resonances
Two planes are also a flat cavity. Energy between them travels at c/√εr and reflects at the edges, and when half a wavelength fits along a side the pair resonates: f = c / (2 L √εr), 723 MHz for a 100 mm side on FR-4. Near a resonance the impedance between the planes is high at the edges and low in the middle, and the edges radiate. Below about a tenth of the first resonance the pair is a lumped capacitor and the formula above tells the whole story; above it, the impedance depends on where the chip sits. A thinner spacing lowers every peak, and capacitors near the edges damp them.
In the stack-up
Four-layer boards usually put ground on layer 2 and power on layer 3 with the thick core between them, which gives little capacitance; the alternative, signal–ground–power–signal with a thin prepreg between the planes, gives far more at the cost of thicker outer dielectrics. Six and eight-layer boards can afford an adjacent power–ground pair on a 0.1 mm or thinner prepreg. Embedded-capacitance laminates go to 8–25 µm with high-εr fillers and reach nanofarads per square inch. Whatever the spacing, keep the planes unbroken under the parts that need them.
Your planes, step by step
- Area: 100 mm × 100 mm = 100 cm².
- Capacitance: 8.854 pF/m × 4.3 × 0.01 m² / 0.1 mm = 3.81 nF (38.1 pF per cm², 3.81 nF with fringing).
- Cavity: 723 MHz along the length, 723 MHz along the width; lumped below 72.3 MHz; |Z| = 83.6 mΩ at 500 MHz, beyond the lumped range.
Worked example: 100 × 100 mm planes on a 0.1 mm FR-4 prepreg
The overlap is 100 cm². With εr 4.3 and 0.1 mm between the planes, C = 8.854 pF/m × 4.3 × 0.01 m² / 0.0001 m = 3.81 nF, 38.1 pF per square centimetre; fringing adds only 0.1%. At 500 MHz that is 83.6 mΩ, lower than any discrete capacitor manages there. The first cavity resonance is at 723 MHz, so the pair is a plain capacitor up to about 72.3 MHz and a cavity with peaks and nulls above it. The same planes on a 1 mm core would hold only 381 pF; for 10 nF on this area the spacing would have to be 38.1 µm, an embedded-capacitance laminate.
Questions
Does the plane capacitance replace decoupling capacitors?
No. It takes over above a few hundred megahertz where capacitors fail; below that the capacitors supply the charge. The two together give a flat impedance across the band.
Which εr should I use at high frequency?
FR-4 drops from about 4.3 at low frequency to 4.0 above a gigahertz; use the laminate's data-sheet value at the frequency that matters. The difference is under 10 %.
Can I use the capacitance in a filter calculation?
As a lumped value only below the lumped limit; beyond it the planes are a distributed structure and a lumped C is wrong by the position-dependent impedance.
What about a two-layer board?
Ground pour against a power pour across 1.6 mm of FR-4 is only a couple of picofarads per square centimetre, too little to matter; two-layer boards rely on capacitors and short loops.