Thermal via arrays: how a via conducts heat, how many you need, fills and solder wicking, and a worked example
The exposed pad under a QFN, a DPAK's tab or an LED's thermal pad can only shed heat through the board, and FR-4 conducts a thousand times worse than copper. A grid of plated vias under the pad punches copper paths through to a plane or a pour on the other side; each is a thin tube of copper, each is worth about 190 °C/W on its own through a 1.6 mm board, and it is the count that does the work. This calculator takes the pad, the drill, the pitch, the plating, the board and the fill, works out how many vias fit, each via's resistance through its barrel and its fill, the array's, the FR-4 left between the vias, the pad-to-plane resistance and the improvement over bare FR-4, the temperature rise for a power and the vias a target needs, with the grid drawn from above and the barrels in cross-section.
How to use the thermal via calculator
- Type the pad's length and width and the keep-in from its edge (0.15–0.3 mm keeps the holes under the tab).
- Type the via drill and pitch, and pick the fill, the plating and the board thickness in the menu row. The vias that fit, each one's resistance, the array's and the pad-to-plane figure appear.
- Add the power for the rise across the board and a target resistance for the vias it needs. The Pitch table tab compares the common pitches with a Use button each.
One via
θvia = tboard / (kCu · π tp (d − tp))
A plated via is a tube of copper, and heat runs down it as current would: the resistance is the length over the conductivity times the cross-section, and the cross-section of a tube is its circumference times its wall, π t (d − t). For a 0.3 mm hole plated 25 µm that is 0.0216 mm² of copper, and through a 1.6 mm board the via is 192.4 °C/W. A bigger hole helps in proportion to its diameter, a thicker plating in proportion to its thickness, a thinner board in proportion to its thickness; none of them changes the order of magnitude. What fills the hole conducts in parallel: solder, if it wicks in, roughly halves the figure; plated copper fill turns the tube into a post at 58.8 °C/W.
The array
Vias in parallel divide the resistance by their count, so an array of twenty-five is twenty-five times better than one, and the FR-4 left between them adds a little more in parallel, a thousand times worse per area but over most of the pad. The result is the resistance from the pad on top of the board to the copper beneath it: for the standard grid of 0.3 mm vias at 1 mm pitch under a 5 mm pad it is about 7.4 °C/W, against 213.3 °C/W for the bare FR-4, so the board has become almost transparent and the pad sits only a few degrees above the plane. What the plane or the back pour then does with the heat is the next question, and the copper pour calculator's job.
Fills and wicking
An open via in a pad has a problem that has nothing to do with heat: at reflow the molten solder on the pad wicks down the hole and leaves the joint short, sometimes with the part tilted. Holes of 0.3 mm and under mostly fill and stop, which is why that size is the standard; larger ones should be tented with mask from the back side, or filled. Solder that does fill a via is a free improvement. Filled-and-capped vias (via-in-pad, plated over with copper) are solid posts, several times better than open ones and flat enough to place a part on, at a cost of a few dollars per board; conductive epoxy fill is for planarity rather than heat, since its conductivity is closer to FR-4 than to copper.
Rules of thumb
0.3 mm holes at 1.0–1.2 mm pitch, 0.2 mm in from the pad's edge, is the grid most datasheets draw and most fabs make without comment: nine under a 3 mm pad, twenty-five under 5 mm. Tighter pitches leave too little web between holes for the drill and take copper from the joint; keep the web at 0.3 mm or more. Many small vias beat a few large ones, both thermally and for wicking. On a multilayer board connect the vias to the ground plane with full thermal contact, not thermal-relief spokes, and put a pour on the back as large as the layout allows; a 1.6 mm board with a good array and a 25 × 25 mm back pour is the cheapest heatsink on the board.
Your array, step by step
- Fit: 5 × 5 = 25 vias of 0.3 mm at 1 mm inside the keep-in.
- Each via: barrel 0.0216 mm² → 192.4 °C/W → 192.4 °C/W.
- Array: 192.4 °C/W / 25 = 7.7 °C/W, with the FR-4 between (229.6 °C/W) → 7.4 °C/W pad to plane, 28.6 × better than bare FR-4.
- Rise: 2 W × 7.4 °C/W = 14.9 °C; 5 °C/W needs 38 vias, more than fit.
Worked example: a QFN's 5 × 5 mm pad
A QFN dissipating 2 W through a 5 × 5 mm exposed pad on a 1.6 mm two-layer board, with 0.3 mm vias plated 25 µm at 1 mm pitch, 0.2 mm in from the edge, and the vias left open. The grid fits ⌊(5 − 0.4 − 0.3) / 1⌋ + 1 = 5 across, 25 vias. Each barrel is π × 0.025 × 0.275 = 0.0216 mm² of copper, so each via is 1.6 mm / (385 × 0.0216 mm²) = 192.4 °C/W, and the 25 in parallel are 7.7 °C/W. The FR-4 left between them, 23.233 mm², is 229.6 °C/W in parallel, so the pad reaches the back copper at 7.4 °C/W, 28.6 times better than the 213.3 °C/W of bare FR-4; the 2 W raise the pad only 14.9 °C above the plane. With the vias solder-filled each becomes 143.3 °C/W and the pad-to-plane figure 5.6 °C/W; copper-filled, 2.3 °C/W. A target of 5 °C/W needs 38 open vias, so the standard grid meets it; the harder problem is now the back pour that has to shed 2 W to the air.
Questions
How many thermal vias does a QFN need?
As many 0.3 mm vias at 1 mm pitch as fit under the pad: nine under a 3 mm pad, sixteen under 4 mm, twenty-five under 5 mm. Beyond that the board is nearly transparent and the plane or pour beneath is the limit.
Should thermal vias be in the pad or next to it?
In the pad: heat enters the board where the part's tab touches it, and a via a millimetre to the side only gets the heat that first spreads through the thin pad copper. Vias in pads bring the wicking problem, which 0.3 mm holes, tenting from the back, or filling solves.
Do thermal vias need thermal reliefs?
No: connect them to the planes with full contact. Reliefs are for pins that must be hand-soldered; a thermal via's whole purpose is the opposite.
What about a four-layer board?
The vias reach the inner ground plane after a fraction of the board's thickness, so their resistance to it is lower than the full-thickness figure here, and the plane spreads the heat over the whole board. Enter the depth to the plane as the board thickness for that case.