Via inductance: why it matters, the formulas, decoupling and ground bounce, and a worked example
A via is a short piece of wire standing on end, and a piece of wire is an inductor: about a nanohenry for a via through a standard 1.6 mm board. That is nothing at low frequency and everything for a fast edge, where it decides how well a decoupling capacitor works and how far a chip's ground lifts when its outputs switch. This calculator gives the inductance from the via's length and drill, the pad-to-antipad capacitance and the via's own impedance and delay, the inductance of several vias in parallel, the reactance at a frequency and the voltage a current edge drops across it, with the via drawn in cross-section between its planes.
How to use the via inductance calculator
- Type the via's length (the board thickness for a through via, the depth for a blind one) and the drill.
- Add the pad and antipad diameters for the capacitance and the via's impedance; the substrate in the menu row sets εr.
- Set how many vias are in parallel, a frequency for the reactance, and a current step and rise time for the voltage across the via. The Length table tab compares the common via lengths.
Why via inductance matters
An inductance drops a voltage proportional to how fast the current through it changes: V = L ΔI/Δt. One nanohenry with an amp switching in a nanosecond is a volt. The currents a modern chip draws from its decoupling capacitors change that fast, so the via between the capacitor and the plane can drop more than the capacitor's own impedance; the same via on a ground pin lifts the chip's ground reference above the board's, which is ground bounce. At a gigahertz a nanohenry is 6 Ω, enough to turn a good capacitor into a poor one. The via's length is what sets it, and nothing else on the board is as easy to overlook.
The formulas
L = 0.2 h [ln(4h/d) + 1] nH C = 1.41 εr T D₁ / (D₂ − D₁) pF
The inductance is Johnson and Graham's rule for a round conductor of length h and diameter d between two planes (5.08 h [ln(4h/d) + 1] with inches); it is within 20 % of measurements, which is as close as the planes' actual positions allow. The capacitance is their rule for the pads of diameter D₁ in an antipad of D₂ through a board T inches thick with dielectric constant εr. The two make the via a short line section of impedance √(L/C) and delay √(LC): a 0.3 mm via through 1.6 mm with a 0.6 mm pad in a 1 mm antipad comes out near 50 Ω, which is why such vias are tolerable in signal paths. Vias in parallel divide the inductance by their number when they are a few diameters apart.
Decoupling and ground bounce
A decoupling capacitor's job is to supply the chip's switching current without the rail dipping, and its path to the planes is a loop: pad, via, plane, via, pad. The vias are often the largest inductance in that loop, so put them in or beside the pads, use two per pad on the noisiest rails, and keep the planes close to the surface so the vias are short. For ground pins the same inductance shows up as bounce, and the cure is the same: more vias, shorter vias, and a plane directly under the chip. A field of vias under a thermal pad does both jobs at once.
Vias in signal paths
For a signal changing layers the via is a small discontinuity whose impedance is √(L/C); a bigger antipad raises it, a bigger pad lowers it, and removing the unused pads on inner layers reduces the capacitance. The unused stub of a through via below the layer it serves is a worse problem at multi-gigabit rates, where back-drilling or blind vias remove it. Give the return current a path too: a ground via next to every signal via that changes reference planes.
Your via, step by step
- Inductance: 0.2 × 1.6 × [ln(21.3) + 1] = 1.3 nH; 1 Ω at 122 MHz.
- Capacitance: 0.57 pF; the via's impedance √(L/C) = 47.6 Ω, delay 27.3 ps.
- At 1 GHz: 8.16 Ω.
- Edge of 1 A in 1 ns: 1.3 V across the via.
Worked example: a 0.3 mm via through a 1.6 mm board
4h/d = 21.3, ln 21.3 = 3.06, so L = 0.2 × 1.6 × 4.06 = 1.3 nH: the rule of a nanohenry per millimetre, give or take. With a 0.6 mm pad in a 1.0 mm antipad on FR-4 the capacitance is 0.57 pF, the via's impedance √(L/C) = 47.6 Ω and its delay 27.3 ps, close enough to a 50 Ω line to pass a fast edge with a small bump. Its reactance reaches 1 Ω at 122 MHz and is 8.16 Ω at 1 GHz. An amp switching in a nanosecond drops 1.3 V across it: with two such vias in parallel that halves to 650 mV, and through a 0.2 mm microvia the same edge would drop only 123 mV.
Questions
Why does the drill size matter so little?
The inductance depends on the logarithm of the diameter: quadrupling the drill removes about 0.28 nH per millimetre of length. Length is linear, diameter is logarithmic.
Do vias in parallel really divide the inductance?
Only when they are spaced a few diameters apart; packed edge to edge their fields overlap and two vias may give only two-thirds of the benefit. Spread stitching vias out.
Is the capacitance formula needed for a power via?
No; it matters for signal vias, where L and C together set the via's impedance. For decoupling and ground the inductance alone tells the story.
How accurate is this?
About 20 %: the real inductance depends on where the current actually returns, which the formula idealises as planes at the via's ends. Use it to compare options, not to the last picohenry.