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PIC18F45208-bit PIC18 microcontroller with 40/44-pin packages

More memory, flexible clocks and carefully shared peripheral pins.

Manufacturer-referenced

Microchip Technology · PIC18F4520-I/P

PDIP-40DS39631E · 2008

PIC18F4520 is an eight-bit microcontroller with 32 KB of Flash program memory, 1536 bytes of RAM and 256 bytes of data EEPROM. Its PIC18 core adds an eight-by-eight hardware multiplier, interrupt priorities and output latch registers. Up to 36 I/O lines share connections with timers, communication interfaces and a thirteen-channel ADC. The selected F-device operates from 4.2 to 5.5 V; the LF variant has different low-voltage limits. An internal oscillator can supply 31 kHz through 8 MHz, with a PLL option for higher internal-clock operation. A 40 MHz external oscillator gives up to 10 million instruction cycles per second because the instruction clock is FOSC divided by four. The reference circuit uses regulated 5 V, the internal 8 MHz oscillator, both supply pairs, ICSP and a resistor-limited LED on RB0. Firmware must disable unwanted analog functions and configure latches, direction and clock selection. PDIP and TQFP use different physical pin numbers, which the package selector keeps mapped consistently.

Real View

PIC18F4520-I/P black PDIP-40 package with silver contacts and readable marking.
PIC18F4520-I/P · PDIP-40Package illustration

Pinout

PIC18F4520PDIP-40Top view
Select a pin to see its functionPDIP-40 · 40 pins

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3D View

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Reset and programmingAnalog / digital multiplexingPorts and serial peripheralsConnect every supply pinOscillator or digital I/OUnused TQFP leads
PIC18F4520PDIP-40Top view

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1
PIN 1 · Reset and programming

MCLR / VPP / RE3

Reset / programming

Function

Active-low reset and programming voltage input; RE3 is input-only when MCLR is disabled.

How to connect

10 kΩ pull-up to 5 V; preserve ICSP VPP access.

At a glance

8-bit PIC18 microcontroller with 40/44-pin packages

Ports share analog, timing and communication functions; the selected configuration determines which function reaches each pad.

32 KBProgram Flash
1536 bytesData RAM
40 MHzMaximum FOSC
10-bit 13 inputsADC

Operating profile

PIC18F4520-I/P

Package
PDIP-40PIC18F4520-I/P
Selected F-device supply
4.2–5.5 VLF-device limits differ
Industrial range
−40–85°CSelected I-grade parts

CPU and memory

Key parameters and their test conditions

Program Flash
32 KBConditions / notes: 16K 16-bit words; some instructions occupy two words
Data RAM
1536 bytesConditions / notes: Access-bank and banked addressing
Data EEPROM
256 bytesConditions / notes: Nonvolatile application storage
Hardware multiplier
8 × 8 bitsConditions / notes: Single instruction cycle multiply
Return stack
31 levelsConditions / notes: Hardware return-address stack
Instruction clock
FOSC / 4Conditions / notes: Up to 10 MIPS at 40 MHz

Package details

Follows the selected physical package

Manufacturer
Microchip Technology
Part number
PIC18F4520-I/P
Package
PDIP-40
Connections
40 pins
Mounting
Through-hole
Lead pitch
2.54 mm
Package code
PDIP-40
Thermal reference
See operating and package limits

Connections by function

Select a pin to open its function, electrical notes and wiring guidance.

Reset and programming1 pins

Analog / digital multiplexing13 pins

Ports and serial peripherals20 pins

Connect every supply pin4 pins

Oscillator or digital I/O2 pins

Values apply to the stated grade and conditions. Absolute maximum ratings are stress limits.DS39631E · 2008

Power every pair

Connect both VDD and VSS pairs with nearby bypass capacitors.

Choose the clock

Select the internal oscillator and its 8 MHz setting.

Configure the ports

Set analog functions, output latches and direction before running the example.

The 8 MHz internal-clock example has a nominal 2 MHz instruction clock. Toggle every 500 ms for a 1 Hz full blink cycle.

PIC18F4520 compact functional architecture inside its IC outline.
Original teaching illustration; matching named nodes are connected.
PIC18F4520 PDIP supply pairs, reset, ICSP and resistor-limited LED connections.
Original teaching illustration; matching named nodes are connected.

Pin reference

Select a pin to explore its function and connection.

40 pins
PinSignalTypeFunction
MCLR / VPP / RE3Reset / programmingActive-low reset and programming voltage input; RE3 is input-only when MCLR is disabled.
RA0 / AN0GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RA1 / AN1GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RA2 / AN2 / VREF− / CVREFGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RA3 / AN3 / VREF+GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RA4 / T0CKI / C1OUTGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RA5 / AN4 / SS / HLVDIN / C2OUTGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RE0 / RD / AN5GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RE1 / WR / AN6GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RE2 / CS / AN7GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
VDDSupplyPositive supply; connect both VDD pins.
VSSSupplyGround return; connect both VSS pins.
OSC1 / CLKI / RA7Oscillator / GPIOExternal oscillator or GPIO, depending on the oscillator configuration.
OSC2 / CLKO / RA6Oscillator / GPIOExternal oscillator or GPIO, depending on the oscillator configuration.
RC0 / T1OSO / T13CKIGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC1 / T1OSI / CCP2GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC2 / CCP1 / P1AGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC3 / SCK / SCLGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD0 / PSP0GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD1 / PSP1GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD2 / PSP2GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD3 / PSP3GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC4 / SDI / SDAGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC5 / SDOGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC6 / TX / CKGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RC7 / RX / DTGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD4 / PSP4GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD5 / PSP5 / P1BGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD6 / PSP6 / P1CGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RD7 / PSP7 / P1DGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
VSSSupplyGround return; connect both VSS pins.
VDDSupplyPositive supply; connect both VDD pins.
RB0 / INT0 / FLT0 / AN12GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB1 / INT1 / AN10GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB2 / INT2 / AN8GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB3 / AN9 / CCP2GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB4 / KBI0 / AN11GPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB5 / KBI1 / PGMGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB6 / KBI2 / PGCGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
RB7 / KBI3 / PGDGPIO / peripheralMultiplexed port and named peripheral functions. Set direction, analog selection and peripheral routing explicitly.
PDIP-40 · Top view · Select a pin number to inspect its connection.

CPU and memory

Selected PIC18F4520

ParameterValueConditions / notes
Program Flash32 KB16K 16-bit words; some instructions occupy two words
Data RAM1536 bytesAccess-bank and banked addressing
Data EEPROM256 bytesNonvolatile application storage
Hardware multiplier8 × 8 bitsSingle instruction cycle multiply
Return stack31 levelsHardware return-address stack
Instruction clockFOSC / 4Up to 10 MIPS at 40 MHz

Instruction timing and branch costs still matter in software delays.

Supply and reset

F-device industrial selection

ParameterValueConditions / notes
VDD range4.2–5.5 VUse regulated 5 V in this example
PDIP suppliesVDD11/32; VSS12/31Connect and bypass both pairs
TQFP suppliesVDD7/28; VSS6/29Same functions, different physical numbers
MCLR / VPPPDIP1; TQFP1810 kΩ reset pull-up; ICSP access retained
RE3Input-only alternate functionAvailable when MCLR is disabled
Industrial temperature−40 to +85°CI-grade orderables

PIC18LF4520 low-voltage limits must not be substituted for the selected PIC18F4520.

Oscillator choices

Internal oscillator and external options

ParameterValueConditions / notes
Internal oscillator block31 kHz through 8 MHzIRCF selects the nominal frequency
Internal example8 MHz, PLL disabled2 MHz nominal instruction clock
OSCCON example0x72IRCF=111; SCS selects the internal oscillator
Internal PLL optionUp to 32 MHzFollow OSCTUNE and oscillator configuration requirements
Maximum external FOSC40 MHz10 MIPS instruction rate
RA6 / RA7Available with suitable internal-oscillator configurationOSC2/OSC1 share these pads

Use the compiler clock setting and configuration bits that match the actual oscillator.

Ports and analog setup

Avoid inherited assumptions from older PICs

ParameterValueConditions / notes
Maximum I/O36 linesIncludes RE3 input-only and oscillator-pin GPIO when available
TRIS1 input; 0 outputSet the output latch before enabling output
LAT registersUse LATx for output updatesAvoid read-modify-write effects from reading pin levels
All-digital exampleADCON1 = 0x0FAN0 through AN12 become digital
Comparators disabledCMCON = 0x07Example uses ordinary GPIO
PORTB analog resetPBADEN configuration mattersExplicitly initialize ADCON1
CCP2 routingRC1 or RB3Selected by CCP2MX

RA4 and RA5 capabilities must be read from this PIC18 device, not copied from PIC16F877A.

Analog, timers and communication

Multiplexed hardware functions

ParameterValueConditions / notes
ADC10-bit, 13 channelsAN0–AN12; references selectable
ADC acquisitionSet settling and conversion timingDepends on source impedance, clock and reference
Timer08- or 16-bitProgrammable prescaler and clock source
Timer1 / Timer316-bitIndependent timing resources
Timer28-bit with period registerPWM timebase
ECCP1 / CCP2Enhanced PWM plus capture/compare/PWMP1A–P1D share port pads
MSSPSPI or I²CRC3/RC4/RC5 and SS routing
EUSARTSynchronous or asynchronousRC6 TX/CK and RC7 RX/DT
Comparators / HLVDTwo comparators and voltage detectSelected analog functions

One pad cannot perform incompatible peripheral functions simultaneously.

ICSP and configuration

Keep programming paths accessible

ParameterValueConditions / notes
PDIP ICSPVPP1, PGC39, PGD40Add VDD and VSS reference
TQFP ICSPVPP18, PGC16, PGD17Verify the package selector before wiring
LVP entryRB5 / PGMPDIP38; TQFP15
LVP choiceDisable deliberately or define PGMDo not copy PIC16 RB3/PGM wiring
Watchdog / brown-outConfigure intentionallyAn enabled unserviced watchdog resets firmware
Internal-clock setupINTIO configuration with RA6/RA7 as GPIOKeep OSCTUNE PLL disabled for the 8 MHz example

Use a compatible programmer and keep programming voltage separate from normal GPIO levels.

Minimal internal-clock LED circuit

PDIP-40, regulated 5 V

ParameterValueConditions / notes
PowerVDD11/32; VSS12/31100 nF at each pair
ResetMCLR1 with 10 kΩ to 5 VICSP VPP remains available
ClockInternal 8 MHzNo crystal is required for this example
LEDRB0 pin33 → 1 kΩ → red LED → GNDAbout 3 mA for an ideal 2 V LED
Firmware initializationADCON1=0x0F; CMCON=0x07Initialize LATB0, then TRISB0=0
Blink periodToggle LATB0 every 500 ms1 Hz full cycle at the configured clock

The illustration is a firmware teaching circuit; timing readings are nominal and are not a running processor model.

Take it into ProTech

Find PIC18F4520 in the Components Library to place its schematic symbol and connect its pins.

Reference page · circuit simulation model not yet availableOpen ProTech

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