BETASelected packagePDIP-16MCP3008-I/P
8-channel 10-bit SPI ADC
MCP3008 Reference Tables
Search the MCP3008 pin reference and manufacturer-referenced specification tables.
Package view
Physical connections16 pinsPackage-specific numbering
Reference collection8 tables49 parameters & pin functions
Pin reference
Signal names, electrical functions and connection guidance
Physical pin numbers16 pins
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| Pin | Signal | Type | Function & connection |
|---|---|---|---|
| CH0 | Multiplexed analog input | Channel 0; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH1 | Multiplexed analog input | Channel 1; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH2 | Multiplexed analog input | Channel 2; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH3 | Multiplexed analog input | Channel 3; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH4 | Multiplexed analog input | Channel 4; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH5 | Multiplexed analog input | Channel 5; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH6 | Multiplexed analog input | Channel 6; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| CH7 | Multiplexed analog input | Channel 7; selected by the three channel bits in the SPI command.Connection guidanceConnect a low-impedance signal within the selected reference range. Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground. | |
| DGND | Digital ground | Return for the SPI interface.Connection guidanceJoin to the common ground plane. | |
| /CS/SHDN | Active-LOW chip select | LOW starts a serial transaction; HIGH ends it and enters standby.Connection guidanceController chip-select output with a defined HIGH idle state. Return HIGH between conversions. A device powered up with CS LOW needs a HIGH-to-LOW sequence. | |
| DIN | Serial command input | Receives the start bit, single/differential flag and channel address.Connection guidanceController MOSI; data is accepted on rising SCLK edges. | |
| DOUT | Serial conversion output | Returns a null bit followed by ten conversion bits, most significant first.Connection guidanceController MISO. Data changes on falling SCLK edges. DOUT is high impedance when CS is HIGH. | |
| SCLK | Serial clock | Clocks command entry, acquisition and successive approximation.Connection guidanceController SPI clock; use mode 0 or mode 3. Meet the minimum effective conversion clock as well as the voltage-dependent maximum. | |
| AGND | Analog ground | Reference return for the analog conversion.Connection guidanceJoin to DGND using a quiet common ground layout. | |
| VREF | Conversion reference | Defines the input span and the ideal step size VREF / 1024.Connection guidanceA stable low-impedance reference, 0.25 V to VDD. Reference quality and loading affect accuracy; do not leave this pin floating. | |
| VDD | Supply | Powers the converter over 2.7–5.5 V.Connection guidanceRegulated supply with a nearby 1 µF bypass. Match the SPI controller logic levels to this supply. |
No pins match these filters. Try another signal name or reset the filters.
Supply, reference and input limits
MCP3008 · selected industrial grades
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Operating supply | 2.7–5.5 V | ADC and controller logic must be compatible |
| Reference input | 0.25 V to VDD | Low-impedance source; reduced reference affects linearity |
| Single-ended range | 0 to VREF | Measured relative to analog ground |
| Pseudo-differential IN− | −100 to +100 mV | Relative to ground; not a wide common-mode differential input |
| Pseudo-differential IN+ | IN− to IN− + VREF | Observe pin voltage limits as well |
| Selected I-grade ambient | −40 to +85°C | MCP3008-I/P and MCP3008-I/SL |
| Extended SOIC option | −40 to +125°C | Use the corresponding E-grade ordering option |
No specifications match. Try a parameter name or a unit.
The table separates operating conditions from absolute stress limits.
Resolution and accuracy
VDD = VREF = 5 V unless stated
Manufacturer-referenced values8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Resolution | 10 bits | Codes 0–1023 |
| Ideal step | VREF / 1024 | 3.22265625 mV at 3.3 V |
| Integral nonlinearity | ±1 LSB maximum | ±0.5 LSB typical |
| Differential nonlinearity | ±1 LSB maximum | No missing codes over specified temperature |
| Offset error, I grade | ±1.5 LSB maximum | −40 to +85°C |
| Offset error, extended grade | ±1.95 LSB maximum | −40 to +125°C |
| Gain error | ±1 LSB maximum | Manufacturer electrical conditions |
| SINAD | 61 dB typical | 1 kHz signal, 0.1–4.9 V input |
No specifications match. Try a parameter name or a unit.
Ideal arithmetic does not include these device errors.
Acquisition and throughput
Supply-dependent SPI timing
Manufacturer-referenced values9 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Acquisition window | 1.5 SCLK periods | Source impedance must allow settling |
| Conversion | 10 SCLK periods | Excludes command and framing overhead |
| Maximum throughput at 5 V | 200 ksps | 3.6 MHz SPI clock, 18-clock framing |
| Maximum throughput at 3.3 V | 130 ksps | 2.34 MHz, characterized recommendation |
| Maximum throughput at 2.7 V | 75 ksps | 1.35 MHz SPI clock |
| Chip-select HIGH time | 270 ns minimum | Between conversions |
| CS LOW to first rising SCLK | 100 ns minimum | Setup time |
| Input data setup / hold | 50 ns / 50 ns minimum | Around rising SCLK edge |
| Effective conversion clock | At least 10 kHz | Finish after acquisition within 1.2 ms at high temperature |
No specifications match. Try a parameter name or a unit.
The 24-clock byte-oriented example has extra framing overhead; it does not achieve the 18-clock maximum throughput.
Three-byte single-ended transfer
SPI mode 0 or mode 3
Manufacturer-referenced values8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Byte 1 transmitted | 0x01 | Seven leading zeros, then START |
| Byte 2 transmitted | (0x08 | channel) << 4 | SGL = 1 followed by channel D2 D1 D0 |
| Byte 3 transmitted | 0x00 | Clocks out the remaining result |
| Receive byte 1 | Ignore | DOUT not valid result data |
| Receive byte 2 | Keep bits 1:0 | Result bits B9 and B8; discard upper bits |
| Receive byte 3 | Keep all eight bits | B7 through B0 |
| Assemble the result | ((RX1 & 0x03) << 8) | RX2 | RX indices are zero-based |
| After transfer | CS HIGH | DOUT becomes Hi-Z; device enters standby |
No specifications match. Try a parameter name or a unit.
Pseudo-differential mode clears SGL. D2–D0 choose IN+; the other member of its adjacent pair is IN−.
Logic, loading and power
Manufacturer test conditions
Manufacturer-referenced values8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Digital HIGH / LOW input | ≥ 0.7 × VDD / ≤ 0.3 × VDD | Do not assume 3.3 V logic reliably drives a 5 V ADC |
| Output HIGH | ≥ 4.1 V | VDD = 4.5 V; source 1 mA |
| Output LOW | ≤ 0.4 V | VDD = 4.5 V; sink 1 mA |
| Active current at 5 V | 425 µA typical; 550 µA maximum | VREF = 5 V; DOUT unloaded |
| Standby current | 5 nA typical; 2 µA maximum | CS = VDD = 5 V |
| Reference current | 100 µA typical; 150 µA maximum | During conversion |
| Analog leakage | ±1 µA maximum | 0.001 µA typical |
| Sample capacitor | 20 pF typical | Internal sampling-switch resistance ≈ 1 kΩ |
No specifications match. Try a parameter name or a unit.
The detailed electrical table specifies 550 µA maximum active current; use it rather than the older 500 µA feature-summary value.
3.3 V controller circuit
Single-ended channel 0
Manufacturer-referenced values6 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VDD16 and VREF15 | Regulated 3.3 V | Common source; VREF must not float |
| AGND14 and DGND9 | Common ground | Keep analog returns quiet |
| Supply bypass | 1 µF | Close to VDD and ground |
| Analog signal | 0–3.3 V into CH0 pin1 | Low-impedance source; unused channels grounded in the illustration |
| SPI wiring | CS10, DIN11, DOUT12, SCLK13 | Controller CS, MOSI, MISO and SCLK respectively |
| Example SPI clock | 1 MHz, mode 0 | Three bytes per conversion; CS HIGH between transfers |
No specifications match. Try a parameter name or a unit.
Use a compatible 3.3 V controller. Input filters and buffering depend on bandwidth and source impedance.
Absolute maximum ratings
Stress limits only
Manufacturer-referenced values3 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply | 7.0 V maximum | Normal operation: 2.7–5.5 V |
| Any input/output | −0.6 to VDD + 0.6 V | Referenced to ground |
| Storage | −65 to +150°C | Unpowered |
No specifications match. Try a parameter name or a unit.
Absolute maximum ratings are not valid operating targets.
No matching rowsTry a pin name, parameter, unit or test condition, or reset the filters.