Explore MCP3208 pins, signal names, electrical functions and connection guidance for each package.
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Channel 0; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 1; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 2; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 3; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 4; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 5; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 6; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Channel 7; selected by the three channel bits in the SPI command.
Connect a low-impedance signal within the selected reference range.
Single-ended: 0 to VREF. Pseudo-differential pairs are adjacent channels; IN− must stay within ±100 mV of ground.
Return for the SPI interface.
Join to the common ground plane.
LOW starts a serial transaction; HIGH ends it and enters standby.
Controller chip-select output with a defined HIGH idle state.
Return HIGH between conversions. A device powered up with CS LOW needs a HIGH-to-LOW sequence.
Receives the start bit, single/differential flag and channel address.
Controller MOSI; data is accepted on rising SCLK edges.
Returns a null bit followed by twelve conversion bits, most significant first.
Controller MISO.
Data changes on falling SCLK edges. DOUT is high impedance when CS is HIGH.
Clocks command entry, acquisition and successive approximation.
Controller SPI clock; use mode 0 or mode 3.
Meet the minimum effective conversion clock as well as the voltage-dependent maximum.
Reference return for the analog conversion.
Join to DGND using a quiet common ground layout.
Defines the input span and the ideal step size VREF / 4096.
A stable low-impedance reference, 0.25 V to VDD.
Reference quality and loading affect accuracy; do not leave this pin floating.
Powers the converter over 2.7–5.5 V.
Regulated supply with a nearby 1 µF bypass.
Match the SPI controller logic levels to this supply.
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