MCP3208 Specifications
Review MCP3208 electrical specifications, operating conditions and package details.
Key specifications
A multiplexer feeds the sample capacitor. The comparator, reference DAC and successive-approximation register resolve the input voltage before the serial port shifts out twelve bits.
Package details
MCP3208-BI/P · PDIP-16
| Property | Details |
|---|---|
| Manufacturer | Microchip Technology |
| Part number | MCP3208-BI/P |
| Package | PDIP-16 |
| Connections | 16 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | PDIP-16 |
| Thermal reference | θJA 70°C/W · manufacturer package reference |
Supply, reference and channels
Industrial MCP3208-BI reference packages
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VDD | 2.7–5.5 V | Match controller I/O levels to this supply |
| VREF | 0.25 V to VDD | Stable, low-impedance reference; low values affect linearity |
| Single-ended input | 0 to VREF | Relative to AGND |
| Pseudo-differential IN− | −100 to +100 mV | Near ground, not arbitrary common-mode voltage |
| Pseudo-differential IN+ | IN− to IN− + VREF | Also observe physical pin voltage limits |
| Selected ambient range | −40 to +85°C | Industrial I grade |
| Conversions | One channel at a time | Not simultaneous sampling |
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Operating limits are distinct from absolute maximum stress ratings.
Resolution and device error
Manufacturer electrical conditions: VDD=VREF=5 V
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Resolution | 12 bits | 4096 codes; 0…4095 |
| Ideal LSB at 3.3 V | 0.8056640625 mV | VREF / 4096 |
| B-grade INL | ±1 LSB maximum | ±0.75 LSB typical |
| C-grade INL | ±2 LSB maximum | ±1 LSB typical; not the selected B-grade |
| DNL | ±1 LSB maximum | ±0.5 LSB typical; no missing codes |
| Offset error | ±3 LSB maximum | ±1.25 LSB typical |
| Gain error | ±5 LSB maximum | ±1.25 LSB typical |
| SINAD | 72 dB typical | 1 kHz, 0.1–4.9 V input |
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The calculator excludes these errors and external reference uncertainty.
Acquisition and serial timing
Supply-dependent rate and loading
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Acquisition interval | 1.5 clock periods | Source must settle to twelve-bit accuracy |
| Conversion interval | 12 clocks | Additional command/framing clocks are required |
| Maximum rate at 5 V | 100 ksps | 2 MHz serial clock, 20-clock conversion framing |
| Maximum rate at 2.7 V | 50 ksps | 1 MHz serial clock |
| CS HIGH interval | 500 ns minimum | Between conversions |
| CS LOW to first rising clock | 100 ns minimum | Serial setup |
| DIN setup / hold | 50 ns / 50 ns minimum | Around rising clock edge |
| Output valid after falling clock | 200 ns maximum | Manufacturer timing test |
| Minimum effective clock | 10 kHz | Finish the conversion within 1.2 ms after acquisition |
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Three-byte transfers add clocks and CS overhead, so a 1 MHz example remains below 41.7 k conversions per second.
Three-byte conversion command
MCP3208 mode 0 or mode 3
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| Parameter | Value | Conditions / notes |
|---|---|---|
| TX0, single-ended | 0x06 | (channel >> 2) | Five leading zeros, START, SGL and D2 |
| TX1 | (channel & 3) << 6 | D1 and D0, followed by zeros |
| TX2 | 0x00 | Clocks out the remaining result |
| Pseudo-differential TX0 | 0x04 | (channel >> 2) | Clears SGL; adjacent channel is IN− |
| RX0 | Discard | No result bits |
| RX1 | Keep low nibble | B11…B8; discard upper four bits |
| RX2 | Keep all eight bits | B7…B0 |
| Result | ((RX1 & 0x0F) << 8) | RX2 | RX indices are zero-based |
| CH0 example | 06 00 00 → XX X8 00 | Ideal half-scale result 2048 |
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Raise CS between transfers. DOUT becomes high impedance while CS is HIGH.
Logic and current requirements
Use specified test conditions
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Digital input HIGH / LOW | ≥0.7×VDD / ≤0.3×VDD | Do not assume 3.3 V HIGH is valid at a 5 V ADC |
| Active supply current at 5 V | 320 µA typical; 400 µA maximum | VDD=VREF=5 V, DOUT unloaded |
| Active current at 2.7 V | 225 µA typical | VDD=VREF=2.7 V |
| Standby current | 0.5 µA typical; 2 µA maximum | CS=VDD=5 V |
| Reference current while converting | 100 µA typical; 150 µA maximum | Reference must handle dynamic load |
| Analog leakage | ±1 µA maximum | 0.001 µA typical |
| Sampling capacitor / switch | 20 pF / 1 kΩ typical | Source resistance adds acquisition error |
| Package thermal reference | θJA 70°C/W · manufacturer package reference | Board construction changes actual thermal performance |
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Use low-impedance analog sources and separate quiet analog returns from clock current paths.
A 3.3 V channel-zero example
Color-coded SPI circuit and ideal readings
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VDD16 and VREF15 | Regulated 3.3 V | Both connected, reference not floating |
| Grounds | AGND14 and DGND9 | Common ground, quiet layout |
| Supply bypass | 1 µF close to VDD | Manufacturer application guidance |
| Signal input | 1.650 V on CH0 pin1 | Low-impedance source; unused inputs grounded in example |
| Serial connection | CS10, DIN11, DOUT12, CLK13 | CS, MOSI, MISO and SCLK |
| Serial clock | 1 MHz, mode 0 | 24 clocks per example transfer, plus CS HIGH interval |
| Ideal output | 2048 · 0x800 | Nominal half scale |
| Decode voltage | code × VREF / 4096 | A nominal reconstruction, not sub-LSB accuracy |
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The sample is analog; fast or high-impedance sensors may require buffering and filtering.
Connections by function
Select a pin for its function, connection guidance and electrical notes.