Skip to datasheet
8-channel 12-bit SPI ADC

MCP3208 Specifications

Review MCP3208 electrical specifications, operating conditions and package details.

Package view

Key specifications

A multiplexer feeds the sample capacitor. The comparator, reference DAC and successive-approximation register resolve the input voltage before the serial port shifts out twelve bits.

Resolution12 bits · 4096 codes
Analog inputs8 Multiplexed
Supply range2.7–5.5 V
Industrial ambient−40–85 °C

Operating profile

Supply, signals and operating conditions

MCP3208 operating profile
ParameterValueConditions / notes
Selected packagePDIP-16MCP3208-BI/P
Maximum rate at 5 V100ksps · specified conditions
Selected B-grade INL±1LSB maximum
Use these values with the stated grade and test conditions.

Package details

MCP3208-BI/P · PDIP-16

Selected package
Selected MCP3208 physical package
PropertyDetails
ManufacturerMicrochip Technology
Part numberMCP3208-BI/P
PackagePDIP-16
Connections16 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codePDIP-16
Thermal referenceθJA 70°C/W · manufacturer package reference

Supply, reference and channels

Industrial MCP3208-BI reference packages

Scroll sideways to see all columns.

ParameterValueConditions / notes
VDD2.7–5.5 VMatch controller I/O levels to this supply
VREF0.25 V to VDDStable, low-impedance reference; low values affect linearity
Single-ended input0 to VREFRelative to AGND
Pseudo-differential IN−−100 to +100 mVNear ground, not arbitrary common-mode voltage
Pseudo-differential IN+IN− to IN− + VREFAlso observe physical pin voltage limits
Selected ambient range−40 to +85°CIndustrial I grade
ConversionsOne channel at a timeNot simultaneous sampling

Operating limits are distinct from absolute maximum stress ratings.

Resolution and device error

Manufacturer electrical conditions: VDD=VREF=5 V

Scroll sideways to see all columns.

ParameterValueConditions / notes
Resolution12 bits4096 codes; 0…4095
Ideal LSB at 3.3 V0.8056640625 mVVREF / 4096
B-grade INL±1 LSB maximum±0.75 LSB typical
C-grade INL±2 LSB maximum±1 LSB typical; not the selected B-grade
DNL±1 LSB maximum±0.5 LSB typical; no missing codes
Offset error±3 LSB maximum±1.25 LSB typical
Gain error±5 LSB maximum±1.25 LSB typical
SINAD72 dB typical1 kHz, 0.1–4.9 V input

The calculator excludes these errors and external reference uncertainty.

Acquisition and serial timing

Supply-dependent rate and loading

Scroll sideways to see all columns.

ParameterValueConditions / notes
Acquisition interval1.5 clock periodsSource must settle to twelve-bit accuracy
Conversion interval12 clocksAdditional command/framing clocks are required
Maximum rate at 5 V100 ksps2 MHz serial clock, 20-clock conversion framing
Maximum rate at 2.7 V50 ksps1 MHz serial clock
CS HIGH interval500 ns minimumBetween conversions
CS LOW to first rising clock100 ns minimumSerial setup
DIN setup / hold50 ns / 50 ns minimumAround rising clock edge
Output valid after falling clock200 ns maximumManufacturer timing test
Minimum effective clock10 kHzFinish the conversion within 1.2 ms after acquisition

Three-byte transfers add clocks and CS overhead, so a 1 MHz example remains below 41.7 k conversions per second.

Three-byte conversion command

MCP3208 mode 0 or mode 3

Scroll sideways to see all columns.

ParameterValueConditions / notes
TX0, single-ended0x06 | (channel >> 2)Five leading zeros, START, SGL and D2
TX1(channel & 3) << 6D1 and D0, followed by zeros
TX20x00Clocks out the remaining result
Pseudo-differential TX00x04 | (channel >> 2)Clears SGL; adjacent channel is IN−
RX0DiscardNo result bits
RX1Keep low nibbleB11…B8; discard upper four bits
RX2Keep all eight bitsB7…B0
Result((RX1 & 0x0F) << 8) | RX2RX indices are zero-based
CH0 example06 00 00 → XX X8 00Ideal half-scale result 2048

Raise CS between transfers. DOUT becomes high impedance while CS is HIGH.

Logic and current requirements

Use specified test conditions

Scroll sideways to see all columns.

ParameterValueConditions / notes
Digital input HIGH / LOW≥0.7×VDD / ≤0.3×VDDDo not assume 3.3 V HIGH is valid at a 5 V ADC
Active supply current at 5 V320 µA typical; 400 µA maximumVDD=VREF=5 V, DOUT unloaded
Active current at 2.7 V225 µA typicalVDD=VREF=2.7 V
Standby current0.5 µA typical; 2 µA maximumCS=VDD=5 V
Reference current while converting100 µA typical; 150 µA maximumReference must handle dynamic load
Analog leakage±1 µA maximum0.001 µA typical
Sampling capacitor / switch20 pF / 1 kΩ typicalSource resistance adds acquisition error
Package thermal referenceθJA 70°C/W · manufacturer package referenceBoard construction changes actual thermal performance

Use low-impedance analog sources and separate quiet analog returns from clock current paths.

A 3.3 V channel-zero example

Color-coded SPI circuit and ideal readings

Scroll sideways to see all columns.

ParameterValueConditions / notes
VDD16 and VREF15Regulated 3.3 VBoth connected, reference not floating
GroundsAGND14 and DGND9Common ground, quiet layout
Supply bypass1 µF close to VDDManufacturer application guidance
Signal input1.650 V on CH0 pin1Low-impedance source; unused inputs grounded in example
Serial connectionCS10, DIN11, DOUT12, CLK13CS, MOSI, MISO and SCLK
Serial clock1 MHz, mode 024 clocks per example transfer, plus CS HIGH interval
Ideal output2048 · 0x800Nominal half scale
Decode voltagecode × VREF / 4096A nominal reconstruction, not sub-LSB accuracy

The sample is analog; fast or high-impedance sensors may require buffering and filtering.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Channels & reference9 pins

Ground2 pins

Serial controls3 pins

Conversion output1 pin

Supply1 pin

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

Component view