MCP4725 Specifications
Review MCP4725 electrical specifications, operating conditions and package details.
Key specifications
The I²C register selects a resistive-string DAC level. A buffer drives VOUT; EEPROM optionally remembers a startup setting. VDD is both power and reference.
Package details
MCP4725A0T-E/CH · SOT-23-6
| Property | Details |
|---|---|
| Manufacturer | Microchip Technology |
| Part number | MCP4725A0T-E/CH |
| Package | SOT-23-6 |
| Connections | 6 pins |
| Mounting | SMD |
| Lead pitch | 0.95 mm |
| Package code | smd |
| Thermal reference | θJA 190.5°C/W · manufacturer reference |
Operating and interface limits
Extended-temperature grade
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply / DAC reference | 2.7–5.5 V | Same VDD pin for power and conversion scale |
| Operating ambient | −40 to +125°C | Selected E grade |
| Code range | 0–4095 | Unsigned 12-bit code |
| I²C modes | 100 kHz, 400 kHz, 3.4 MHz | High-speed mode requires its specified protocol |
| SDA/SCL input HIGH / LOW | ≥ 0.7 VDD / ≤ 0.3 VDD | Use compatible logic levels |
| A0 input HIGH / LOW | ≥ 0.8 VDD / ≤ 0.2 VDD | Different from SDA/SCL thresholds |
| Supply current | 210 µA typical / 400 µA maximum | Code zero; digital inputs grounded; VOUT unloaded |
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Absolute maximum supply is a stress rating and must not replace the recommended operating range.
Ideal transfer at 3.3 V
VOUT = VDD × code / 4096
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Code 0 / 0x000 | 0 V ideal | Real zero-scale offset remains |
| Code 1 / 0x001 | 0.000805664 V | One ideal LSB |
| Code 1024 / 0x400 | 0.825 V | Quarter-scale |
| Code 2048 / 0x800 | 1.650 V | Midscale example |
| Code 3072 / 0xC00 | 2.475 V | Three-quarter scale |
| Code 4095 / 0xFFF | 3.299194 V | One ideal LSB below VDD |
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A rail-to-rail amplifier is still affected by load and headroom near either supply.
I²C command examples
Selected A0 factory option; external A0 LOW
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Seven-bit address | 0x60 | 0xC0 write / 0xC1 read are address bytes, not seven-bit addresses |
| External A0 HIGH | 0x61 | Other factory options provide the remaining address pairs |
| Fast write, midpoint | Data bytes 0x08 0x00 | PD=00; code=0x800; EEPROM unchanged |
| DAC-register write | Data bytes 0x40 0x80 0x00 | Same code via three-byte command format |
| DAC + EEPROM write | Data bytes 0x60 0x80 0x00 | Intentional persistent startup setting |
| Read sequence | Five data bytes after the address | Current status, DAC code and EEPROM content |
| RDY/BSY status | 1 ready; 0 EEPROM write in progress | Returned status bit; no separate ready pin |
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Do not send new write commands during an EEPROM write. Check the returned ready status first.
EEPROM and power modes
Preserve endurance by choosing the correct command
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| Parameter | Value | Conditions / notes |
|---|---|---|
| EEPROM write duration | 25 ms typical / 50 ms maximum | Poll RDY/BSY rather than assuming immediate completion |
| EEPROM endurance | 1 million cycles minimum at +25°C | Design-assured parameter, not 100% tested |
| Data retention | 200 years typical at +25°C | Temperature and conditions matter |
| Startup | Loads stored code and mode | Observe the specified VDD ramp conditions |
| PD 00 | Normal output buffer | DAC output enabled |
| PD 01 / 10 / 11 | 1 kΩ / 100 kΩ / 500 kΩ to ground | Typical output resistance with amplifier powered down |
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Nonvolatile memory is for remembered settings, not continuous waveform updates.
Accuracy and dynamic behavior
Datasheet test conditions apply
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| Parameter | Value | Conditions / notes |
|---|---|---|
| INL | ±2 LSB typical / ±14.5 LSB maximum | Test codes 100–4000 |
| DNL | ±0.2 LSB typical / ±0.75 LSB limits | Test codes 100–4000 |
| Offset error | 0.02% typical / 0.75% maximum FSR | Code zero |
| Gain error | −0.1% typical / ±2% limits FSR | Code 4095; excludes offset |
| Settling time | 6 µs typical | 0x400→0xC00; within half LSB; RL 5 kΩ, CL 100 pF |
| Supply dependence | VDD is the reference | Supply changes scale every nonzero code |
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Typical values are not guarantees. Resolution and absolute accuracy are different properties.
Midscale voltage-output circuit
3.3 V logic and a high-impedance measurement
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VDD3 / VSS2 | 3.3 V / GND | 100 nF plus 10 µF local bypass |
| A0 pin 6 | GND | Address 0x60 for the selected factory option |
| SDA4 / SCL5 | Controller bus | Example 4.7 kΩ pull-ups to 3.3 V; 100 kHz |
| VOUT1 | High-impedance meter | Meter return joins VSS |
| Write | 0x08, 0x00 after address + W | Fast volatile update, Normal mode |
| Expected output | 1.650 V ideal | Measure actual VDD when checking the result |
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Use a suitable external buffer for loads beyond the DAC output’s intended capability.
Package and layout
MCP4725A0T-E/CH · SOT-23-6
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Lead pitch | 0.95 mm | Six gullwing leads; three on each side |
| Nominal visual body | 1.6 × 2.9 mm | Manufacturer tolerance range applies |
| Original footprint | 1.10 × 0.60 mm lands | 2.70 mm pad-row centers; engineering starting point |
| Top marking | AJ plus trace code for A0 option | Illustration labels identify the device; actual marking is abbreviated |
| Supply bypass | Close to pins 3 and 2 | Keep output and ground paths quiet |
| Load connection | Low leakage, suitable impedance | Avoid long capacitive output wiring |
No specifications match. Try a parameter name or a unit.
Verify the selected package, pad dimensions and assembly process before PCB manufacture.
Connections by function
Select a pin for its function, connection guidance and electrical notes.