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12-bit I²C DAC with EEPROM

MCP4725 Specifications

Review MCP4725 electrical specifications, operating conditions and package details.

Key specifications

The I²C register selects a resistive-string DAC level. A buffer drives VOUT; EEPROM optionally remembers a startup setting. VDD is both power and reference.

Resolution12 bits · 4096 codes
Supply / reference2.7–5.5 V
Typical settling6 µs · specified step/load
Operating ambient−40–125 °C

Operating profile

Supply, signals and operating conditions

MCP4725 operating profile
ParameterValueConditions / notes
Selected packageSOT-23-6MCP4725A0T-E/CH
Step at 3.3 V805.664 µVVDD / 4096
Midscale example1.650 VCode 2048 / 0x800 · ideal
Use these values with the stated grade and test conditions.

Package details

MCP4725A0T-E/CH · SOT-23-6

Selected package
Selected MCP4725 physical package
PropertyDetails
ManufacturerMicrochip Technology
Part numberMCP4725A0T-E/CH
PackageSOT-23-6
Connections6 pins
MountingSMD
Lead pitch0.95 mm
Package codesmd
Thermal referenceθJA 190.5°C/W · manufacturer reference

Operating and interface limits

Extended-temperature grade

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ParameterValueConditions / notes
Supply / DAC reference2.7–5.5 VSame VDD pin for power and conversion scale
Operating ambient−40 to +125°CSelected E grade
Code range0–4095Unsigned 12-bit code
I²C modes100 kHz, 400 kHz, 3.4 MHzHigh-speed mode requires its specified protocol
SDA/SCL input HIGH / LOW≥ 0.7 VDD / ≤ 0.3 VDDUse compatible logic levels
A0 input HIGH / LOW≥ 0.8 VDD / ≤ 0.2 VDDDifferent from SDA/SCL thresholds
Supply current210 µA typical / 400 µA maximumCode zero; digital inputs grounded; VOUT unloaded

Absolute maximum supply is a stress rating and must not replace the recommended operating range.

Ideal transfer at 3.3 V

VOUT = VDD × code / 4096

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ParameterValueConditions / notes
Code 0 / 0x0000 V idealReal zero-scale offset remains
Code 1 / 0x0010.000805664 VOne ideal LSB
Code 1024 / 0x4000.825 VQuarter-scale
Code 2048 / 0x8001.650 VMidscale example
Code 3072 / 0xC002.475 VThree-quarter scale
Code 4095 / 0xFFF3.299194 VOne ideal LSB below VDD

A rail-to-rail amplifier is still affected by load and headroom near either supply.

I²C command examples

Selected A0 factory option; external A0 LOW

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ParameterValueConditions / notes
Seven-bit address0x600xC0 write / 0xC1 read are address bytes, not seven-bit addresses
External A0 HIGH0x61Other factory options provide the remaining address pairs
Fast write, midpointData bytes 0x08 0x00PD=00; code=0x800; EEPROM unchanged
DAC-register writeData bytes 0x40 0x80 0x00Same code via three-byte command format
DAC + EEPROM writeData bytes 0x60 0x80 0x00Intentional persistent startup setting
Read sequenceFive data bytes after the addressCurrent status, DAC code and EEPROM content
RDY/BSY status1 ready; 0 EEPROM write in progressReturned status bit; no separate ready pin

Do not send new write commands during an EEPROM write. Check the returned ready status first.

EEPROM and power modes

Preserve endurance by choosing the correct command

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ParameterValueConditions / notes
EEPROM write duration25 ms typical / 50 ms maximumPoll RDY/BSY rather than assuming immediate completion
EEPROM endurance1 million cycles minimum at +25°CDesign-assured parameter, not 100% tested
Data retention200 years typical at +25°CTemperature and conditions matter
StartupLoads stored code and modeObserve the specified VDD ramp conditions
PD 00Normal output bufferDAC output enabled
PD 01 / 10 / 111 kΩ / 100 kΩ / 500 kΩ to groundTypical output resistance with amplifier powered down

Nonvolatile memory is for remembered settings, not continuous waveform updates.

Accuracy and dynamic behavior

Datasheet test conditions apply

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ParameterValueConditions / notes
INL±2 LSB typical / ±14.5 LSB maximumTest codes 100–4000
DNL±0.2 LSB typical / ±0.75 LSB limitsTest codes 100–4000
Offset error0.02% typical / 0.75% maximum FSRCode zero
Gain error−0.1% typical / ±2% limits FSRCode 4095; excludes offset
Settling time6 µs typical0x400→0xC00; within half LSB; RL 5 kΩ, CL 100 pF
Supply dependenceVDD is the referenceSupply changes scale every nonzero code

Typical values are not guarantees. Resolution and absolute accuracy are different properties.

Midscale voltage-output circuit

3.3 V logic and a high-impedance measurement

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ParameterValueConditions / notes
VDD3 / VSS23.3 V / GND100 nF plus 10 µF local bypass
A0 pin 6GNDAddress 0x60 for the selected factory option
SDA4 / SCL5Controller busExample 4.7 kΩ pull-ups to 3.3 V; 100 kHz
VOUT1High-impedance meterMeter return joins VSS
Write0x08, 0x00 after address + WFast volatile update, Normal mode
Expected output1.650 V idealMeasure actual VDD when checking the result

Use a suitable external buffer for loads beyond the DAC output’s intended capability.

Package and layout

MCP4725A0T-E/CH · SOT-23-6

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ParameterValueConditions / notes
Lead pitch0.95 mmSix gullwing leads; three on each side
Nominal visual body1.6 × 2.9 mmManufacturer tolerance range applies
Original footprint1.10 × 0.60 mm lands2.70 mm pad-row centers; engineering starting point
Top markingAJ plus trace code for A0 optionIllustration labels identify the device; actual marking is abbreviated
Supply bypassClose to pins 3 and 2Keep output and ground paths quiet
Load connectionLow leakage, suitable impedanceAvoid long capacitive output wiring

Verify the selected package, pad dimensions and assembly process before PCB manufacture.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Analog voltage output1 pin

Ground1 pin

Supply1 pin

I²C interface2 pins

Address selection1 pin

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

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