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Precision bipolar operational amplifier

OP07 Specifications

Review OP07 electrical specifications, operating conditions and package details.

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Key specifications

Input offset is only one error term. Include bias-current drops, resistor ratios, thermal gradients and loading before treating a result as accurate.

C-grade typical offset±60 µV ·25°C; not a maximum
Recommended split rails±3–±18 V
Ambient operating range0–70 °C
Typical voltage noise9.8 nV/√Hz ·1 kHz

Operating profile

Supply, signals and operating conditions

OP07 operating profile
ParameterValueConditions / notes
Selected packagePDIP-8OP07CP
Illustrated gain10×90 kΩ/10 kΩ negative feedback
Optional null pins1 and 8NC 5 remains unconnected
Use these values with the stated grade and test conditions.

Package details

OP07CP · PDIP-8

Selected package
Selected OP07 physical package
PropertyDetails
ManufacturerTexas Instruments
Part numberOP07CP
PackagePDIP-8
Connections8 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codedip
Thermal referenceθJA85°C/W on TI reference board

Supply and operating conditions

TI OP07C reference

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ParameterValueConditions / notes
Recommended split supply±3 to±18 V6–36 V total span
Example rails±15 V0 V midpoint is signal ground
Ambient range0–70°CSelected commercial C grade
Common-mode recommended at±15 V−13 to+13 VDo not infer rail-to-rail operation
Absolute supply maximum±22 VStress limit, not an operating target
Input absolute limit noteMagnitude no greater than supply or15 V, whichever is lessManufacturer footnote applies
Local bypass100 nF per rail to 0 VShort return paths near pins 7 and 4

Do not substitute the absolute stress values for recommended operation.

C-grade input accuracy

±15 V,25°C unless stated; column labels retained

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ParameterValueConditions / notes
Input offset voltage±60 µV typical±85 µV typical across0–70°C
Offset drift±0.5 µV/°C typicalC grade; not a guaranteed maximum
Long-term offset drift±0.4 µV/month typical estimateAverage trend after first30 days; not individually guaranteed
Input bias current±1.8 nA typical±2.2 nA typical across0–70°C
Input offset current±0.8 nA typical±1.6 nA typical across0–70°C
Bias-current drift±18 pA/°C typicalC-grade table
Offset adjustment range±4 mV typicalRs20 kΩ; optional manufacturer trim network

TI revision H places these C-grade values in the typical column. They are not maximum-error guarantees.

Noise and rejection

Use the bandwidth and source conditions

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ParameterValueConditions / notes
Voltage noise,0.1–10 Hz0.38 µV peak-to-peak typicalNot RMS
Voltage noise density at10 Hz10.5 nV/√Hz typicalInput-referred
Voltage noise density at1 kHz9.8 nV/√Hz typicalInput-referred
Current noise density at1 kHz0.13 pA/√Hz typicalSource resistance converts it to voltage noise
C-grade CMRR at25°C100 dB minimum;120 dB typicalVCM±13 V
C-grade CMRR over0–70°C97 dB minimum;120 dB typicalVCM±13 V
Supply sensitivity at25°C7 µV/V typical;32 µV/V maximumVS±3 to±18 V
Supply sensitivity over0–70°C10 µV/V typical;51 µV/V maximumLower is better; table usesµV/V

Noise densities must be integrated over the circuit bandwidth.

Speed, loading and power

Manufacturer test conditions

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ParameterValueConditions / notes
Unity-gain bandwidth0.4 MHz minimum;0.6 MHz typicalStandard table conditions
Slew rate0.3 V/µs typicalVS5 V;RL2 kΩ per source table
Output swing at25°C,RL2 kΩ±11.5 V minimum;±12.8 V typicalVS±15 V
Output swing over0–70°C,RL2 kΩ±11 V minimum;±12.6 V typicalVS±15 V
Output swing atRL10 kΩ±12 V minimum;±13 V typicalVS±15 V
No-load device power at±15 V80 mW typical;150 mW maximumNot output power
No-load device power at±3 V4 mW typical;8 mW maximumLower-supply condition

Check headroom and settling; this is not a high-speed amplifier.

Gain-of-ten precision example

Calculated DC illustration

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ParameterValueConditions / notes
VIN0.20 VNon-inverting pin 3
Feedback resistor90 kΩOUT 6 to IN− 2
Ground resistor10 kΩIN− 2 to 0 V midpoint
Ideal gain10 V/V1+90/10
Ideal output2.00 V0.20×10
Typical offset contributionAbout0.60 mV at output60 µV×noise gain 10; not total error
Unused trim / NC1 and 8 open; 5 unconnectedOptional offset adjustment omitted

Select resistor ratio tolerance for the required accuracy; the illustration is not calibrated hardware.

Package pins and board practice

OP07CP ·PDIP-8

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ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
Input pair2 IN−;3 IN+Keep leakage and contamination low
Supply4 V−;7 V+Both locally bypassed
Output6Return feedback close to the input network
Optional trim1 NULL1;8 NULL2Follow the exact manufacturer circuit
No connection5Leave open
Thermal layoutAvoid uneven heating near input nodesThermoelectric voltages can matter at µV levels

Top view, counterclockwise numbering; pin 1 at the marker.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Optional offset trim2 pins

Signal inputs2 pins

Supply2 pins

Not connected1 pin

Analog output1 pin

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

Component view