BETASelected packagePDIP-16SG3525AN
Alternating-output PWM controller
SG3525A Reference Tables
Search the SG3525A pin reference and manufacturer-referenced specification tables.
Package view
Physical connections16 pinsPackage-specific numbering
Reference collection8 tables52 parameters & pin functions
Pin reference
Signal names, electrical functions and connection guidance
Physical pin numbers16 pins
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| Pin | Signal | Type | Function & connection |
|---|---|---|---|
| INV | Inverting error input | A higher voltage than NI2 reduces the demand for output conduction.Connection guidanceConnect to the midpoint of two 10 kΩ resistors from REF16 to GND in this pulse demonstration. | |
| NI | Noninverting error input | A higher voltage than INV1 requests a longer pulse.Connection guidanceConnect to REF16 for maximum pulse demand in the bench example. The amplifier inputs are biased in the documented common-mode region, not left floating. | |
| SYNC | Oscillator synchronization input | External positive clock pulses can synchronize the oscillator.Connection guidanceTie to GND when not using external synchronization. | |
| OSC OUT | Oscillator clock output | Clock at the oscillator rate, before alternating output steering.Connection guidanceLeave open or use a high-impedance scope. | |
| CT | Timing capacitor node | The oscillator charges and discharges this external capacitor.Connection guidanceConnect 10 nF to GND and RD = 100 Ω to DISCHARGE7. | |
| RT | Timing resistor node | Sets the oscillator charging current.Connection guidanceConnect 10 kΩ to GND. | |
| DISCHARGE | Timing discharge contact | The external resistance between this pin and CT sets extra discharge dead time.Connection guidanceConnect 100 Ω between pins 7 and 5. RD belongs between DISCHARGE and CT, not from pin 7 to ground. | |
| SOFT START | Soft-start capacitor node | An internal current charges the capacitor and gradually releases the pulse-width limit.Connection guidanceConnect 1 µF to GND, positive at pin 8 if polarized. Shutdown and undervoltage lockout discharge this capacitor. | |
| COMP | Error-amplifier compensation | Error-amplifier output and PWM control node. External compensation shapes a real regulator loop.Connection guidanceLeave externally unconnected for this fixed-demand scope example. An external pull-down can suppress pulses; do not force a voltage against the amplifier output. | |
| SHUTDOWN | Active-HIGH shutdown | A positive input turns both outputs off; a sustained command discharges soft start.Connection guidanceUse 10 kΩ to GND and a normally open pushbutton to REF16. Do not leave this pin floating. | |
| OUT A | First alternating output | Totem-pole output driven from VC13. LOW is the OFF state.Connection guidanceUse a high-impedance scope and an optional 10 kΩ load to GND. | |
| GND | Common return | Return for the control supply, reference, oscillator and output drivers.Connection guidanceJoin supply bypass and timing returns close to this pin. | |
| VC | Output-driver supply | Separate supply for the two output stages.Connection guidanceConnect to +12 V with local 100 nF bypass in the bench circuit. It is a supply input, not a switch output. | |
| OUT B | Second alternating output | Receives alternate oscillator cycles relative to OUT A. LOW is the OFF state.Connection guidanceUse the second scope channel and an optional 10 kΩ load to GND. | |
| VI | Control supply | Powers the reference and internal control circuitry.Connection guidanceConnect +12 V with 100 nF and local bulk decoupling. | |
| VREF | 5.1 V reference | Bias reference for low-current control networks.Connection guidanceBypass with 100 nF; feed NI2, the INV divider and the shutdown switch. Use the SG3525A electrical table: initial output is specified 5.0–5.2 V. |
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Recommended operating region
ST SG3525A
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Control supply VI | 8–35 V | Pin 15 |
| Driver supply VC | 4.5–35 V | Pin 13; separate driver supply |
| Ambient temperature | 0 to +70°C | SG3525A; do not substitute SG2525A limits |
| Oscillator frequency | 100 Hz–400 kHz | Recommended conditions table |
| Steady output load | 0–100 mA source or sink | Per output; thermal design still applies |
| Peak output load | 0–400 mA | Peak operation only |
| Reference load | 0–20 mA | External control bias |
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The operating table is used here; the front-page frequency headline is broader.
Oscillator and PWM
External components set the rate
Manufacturer-referenced values8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| RT | 2–150 kΩ | Pin 6 to GND |
| CT | 1–100 nF | Pin 5 to GND |
| RD | 0–500 Ω | Between pins 5 and 7 |
| Frequency equation | fOSC ≈ 1 / [CT × (0.7 RT + 3 RD)] | First-order approximation |
| Output repetition | fA = fB = fOSC / 2 | Alternating cycles |
| Maximum duty per output | 45% minimum capability; 49% typical | Manufacturer test setup |
| PWM zero-duty threshold | 0.7 V minimum; 0.9 V typical | Control threshold, not shutdown-pin threshold |
| PWM maximum-duty threshold | 3.3 V typical; 3.6 V maximum | Specified test conditions |
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Timing tolerances and propagation effects matter; calculated values are not measured guarantees.
Reference and amplifier
Keep bias within the valid region
Manufacturer-referenced values6 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Initial reference | 5.0–5.2 V; 5.1 V typical | SG3525A at TJ = 25°C |
| Total reference variation | 4.95–5.25 V | Specified line, load and temperature |
| Amplifier offset | 2 mV typical; 10 mV maximum | Specified test conditions |
| Open-loop gain | 75 dB typical; 60 dB minimum | RL ≥ 10 MΩ |
| Common-mode test region | 1.5–5.2 V | Manufacturer rejection-ratio test |
| Example input bias | INV ≈ 2.55 V; NI ≈ 5.1 V | Requests maximum pulse width after soft start |
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Pin 9 is an amplifier output; external forcing must account for its internal drive.
Soft start and shutdown
Two ways to inhibit pulses
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Soft-start charging current | 25–80 µA; 50 µA typical | VSD = 0 V, VSS = 0 V |
| Shutdown threshold | 0.6–1.0 V; 0.8 V typical | Output shutdown test at TJ = 25°C |
| Shutdown input current | 0.4 mA typical; 1 mA maximum | VSD = 2.5 V |
| Short shutdown pulse | Terminates the current PWM pulse | May not substantially discharge CSS |
| Long shutdown command | Discharges CSS | Soft start repeats after release |
| UVLO threshold | 6–8 V; 7 V typical | Specified test with COMP and SS HIGH |
| Off state | OUT A = LOW; OUT B = LOW | SG3525A logic |
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Keep shutdown defined. It is not a general-purpose power-stage fault detector without external sensing.
12 V scope circuit
No high-power switching stage
Manufacturer-referenced values10 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VI15 and VC13 | +12 V | 100 nF at each rail plus local bulk bypass |
| GND12 | Common ground | Short control and bypass returns |
| REF16 | 100 nF bypass | Feeds NI2, shutdown switch and divider |
| INV1 | REF / 2 | Two 10 kΩ divider resistors |
| NI2 / COMP9 | REF / no external connection | Requests full available PWM; soft start still limits startup |
| SYNC3 / OSC OUT4 | GND / open | Free-running oscillator; optional clock probe |
| RT6 / CT5 | 10 kΩ / 10 nF to GND | RD = 100 Ω from CT5 to DISCHARGE7 |
| SOFT START8 | 1 µF to GND | Positive at pin 8 if polarized |
| SHUTDOWN10 | 10 kΩ to GND | Normally open pushbutton connects it to REF16 |
| OUT A11 / OUT B14 | Separate high-impedance scope channels | Optional 10 kΩ load from each output to ground |
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Do not connect outputs together; their active intervals alternate.
Example readings
Nominal calculated values
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Oscillator period | 10 nF × (0.7 × 10 kΩ + 3 × 100 Ω) = 73 µs | First-order estimate |
| Oscillator frequency | Approximately 13.70 kHz | Inverse of 73 µs |
| Each output frequency | Approximately 6.85 kHz | Half the oscillator rate |
| Each output period | Approximately 146 µs | Alternating cycle allocation |
| Divider load | 5.1 V / 20 kΩ = 0.255 mA | Nominal reference |
| Soft-start slope | 50 µA / 1 µF = 50 V/s | Typical initial slope |
| Soft-start voltage change | 1 V in about 20 ms | Not a guaranteed complete startup time |
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Real startup also depends on amplifier demand, capacitor tolerance, charging current and PWM thresholds.
Packages and stress limits
SG3525AN · PDIP-16
Manufacturer-referenced values7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Through-hole | SG3525AN · DIP16 | 2.54 mm lead pitch |
| Surface mount | SG3525AP · narrow SO16 | 1.27 mm lead pitch |
| VI / VC absolute maximum | 40 V | Stress rating, not normal operating voltage |
| Output absolute maximum | 500 mA | Do not treat as a continuous drive rating |
| Reference absolute maximum | 50 mA | Recommended external load is lower |
| Storage temperature | −65 to +150°C | Unpowered |
| Logic-input absolute range | −0.3 to +5.5 V | Do not apply the 12 V rail to shutdown or sync |
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Footprints are editable starting land patterns; validate clearances and the purchased package before fabrication.
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