TL494 Specifications
Review TL494 electrical specifications, operating conditions and package details.
Key specifications
The error amplifiers and dead-time input can each reduce the output conduction interval. Output mode determines whether the two channels pulse together or alternate.
Package details
TL494CN · PDIP-16
| Property | Details |
|---|---|
| Manufacturer | Texas Instruments |
| Part number | TL494CN |
| Package | PDIP-16 |
| Connections | 16 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | PDIP-16 |
| Thermal reference | See operating and package limits |
Operating conditions
TL494C selected variants
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Control supply | 7–40 V | 12 V bench circuit |
| Ambient temperature | 0 to +70°C | C grade; I grade is a different ordering choice |
| Oscillator frequency | 1–300 kHz | Recommended range |
| Timing resistor | 1.8–500 kΩ | RT to ground |
| Timing capacitor | 0.47–10000 nF | CT to ground |
| Amplifier input common mode | −0.3 V to VCC−2 V | Do not exceed the valid range |
| Output current | Up to 200 mA per transistor | Check voltage drop, thermal conditions and external limits |
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Output current capability does not mean the IC includes a safe power-stage current limiter.
Reference and feedback
Specified test conditions
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| Parameter | Value | Conditions / notes |
|---|---|---|
| REF at 1 mA | 4.75–5.25 V; 5 V typical | Specified supply and temperature conditions |
| Reference external load | Up to 10 mA available for bias | Includes the potentiometer and other external loads |
| Feedback input sink | 0.3 mA minimum, 0.7 mA typical | FEEDBACK = 0.7 V |
| PWM zero-duty threshold | 3.4 V typical, 4.5 V maximum | Feedback control test |
| Error amplifier offset | 2 mV typical, 10 mV maximum | Specified electrical test |
| Error amplifier gain | 80 dB typical, 70 dB minimum | Specified load and output range |
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The reference is for control bias; it is not a general-purpose supply rail.
Output modes
Configure OUTPUT CTRL as a fixed logic level
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Pin 13 to GND | Single-ended / simultaneous | Both outputs can conduct during the same oscillator cycle |
| Pin 13 to REF | Push-pull / alternating | Each output receives every other oscillator cycle |
| Single-ended frequency | fOUT ≈ fOSC | Same period per channel |
| Push-pull frequency | fOUT ≈ fOSC / 2 | Twice the period per channel |
| Grounded DTC | Maximum allowed conduction | Internal blanking still prevents an ideal 100% duty |
| Increasing DTC | Shorter conduction pulses | Around 3.3 V can command zero duty under specified conditions |
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At the pulled-up C outputs used here, transistor conduction appears as a LOW pulse.
Resistor-loaded pulse circuit
No external power stage
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VCC12 / GND7 | +12 V / common GND | 100 nF and local bulk bypass |
| REF14 | 100 nF to GND | Feeds both inverting amplifier inputs and 10 kΩ pot |
| Amplifier inputs | 1 / 16 to GND; 2 / 15 to REF | Keeps the error amplifiers from demanding shutdown |
| FEEDBACK3 | No external connection | Internal amplifier/bias network still determines its voltage |
| DTC4 | Potentiometer wiper | Pot ends REF and GND; start HIGH |
| CT5 / RT6 | 1 nF / 100 kΩ to GND | Nominal 10 kHz design equation |
| Mode13 | GND | Simultaneous operation |
| Outputs | E1-9 / E2-10 to GND | C1-8 and C2-11 each pull up to +12 V through 4.7 kΩ |
| Measurement | High-impedance two-channel scope | Observe each C output relative to GND |
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Do not attach a motor or transformer to this demonstration; output loads are deliberately small.
Frequency and example calculations
First-order design values
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Oscillator | 1/(100000 Ω × 1 nF) = 10 kHz | Nominal approximation |
| Oscillator period | 100 µs | Inverse of 10 kHz |
| Single-ended output period | 100 µs | Same as oscillator |
| Push-pull per-output period | 200 µs | 5 kHz on each output |
| Approximate pulled-up load | 12 V / 4.7 kΩ = 2.55 mA | Ignoring switch voltage drop |
| Worst resistor power at continuous ON | 12² / 4700 ≈ 31 mW | Use suitable voltage and power ratings |
| Potentiometer reference load | 5 V / 10 kΩ = 0.5 mA | Plus other reference loads |
No specifications match. Try a parameter name or a unit.
Real timing varies with component tolerances and oscillator characteristics.
Layout and integration
Keep control wiring distinct from a power stage
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Timing loop | Short CT/RT ground return | Keep away from switching nodes |
| Reference bypass | Close to REF14 and GND7 | Avoid loading the reference excessively |
| Supply bypass | Close to VCC12 and GND7 | Add suitable local bulk capacitance |
| Feedback compensation | Application-specific | Needed for stable closed-loop regulation |
| Output polarity | LOW at C when sinking | An external follower connection has a different waveform |
| Power switch drive | Separate design task | Check gate charge, edge speed and protection |
No specifications match. Try a parameter name or a unit.
A clear bench waveform alone does not validate a complete switching converter.
Package and stress limits
TL494CN · PDIP-16
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| Parameter | Value | Conditions / notes |
|---|---|---|
| PDIP | TL494CN · N package | 16 pins, 2.54 mm pitch |
| SOIC | TL494CDR · D package | 16 pins, 1.27 mm pitch |
| Supply stress | 41 V absolute maximum | Normal operation maximum is 40 V |
| Output current stress | 250 mA absolute maximum | Recommended current maximum is 200 mA with conditions |
| Storage | −65 to +150°C | Unpowered |
| Outputs C/E | Keep the manufacturer pin names | The current revision describes the switching output implementation separately from legacy terminology |
No specifications match. Try a parameter name or a unit.
Use the selected orderable and datasheet revision rather than mixing limits from different manufacturers.
Connections by function
Select a pin for its function, connection guidance and electrical notes.