GND
Function
Supply and segment-current return.
How to connect
Connect to the common ground and the bypass capacitors.
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Supply and segment-current return.
Connect to the common ground and the bypass capacitors.
Sinks current from segment 1; also provides key-scan timing.
Connect to the shared cathodes of segment A across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 2; also provides key-scan timing.
Connect to the shared cathodes of segment B across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 3; also provides key-scan timing.
Connect to the shared cathodes of segment C across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 4; also provides key-scan timing.
Connect to the shared cathodes of segment D across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 5; also provides key-scan timing.
Connect to the shared cathodes of segment E across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 6; also provides key-scan timing.
Connect to the shared cathodes of segment F across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 7; also provides key-scan timing.
Connect to the shared cathodes of segment G across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Sinks current from segment 8; also provides key-scan timing.
Connect to the shared cathodes of segment DP across the display.
A set display bit enables the corresponding sink during the selected grid slot.
Drives the common anode of digit 6.
Connect to the common anode of display digit 6.
Use common-anode LEDs; these outputs are not logic-level GPIO.
Drives the common anode of digit 5.
Connect to the common anode of display digit 5.
Use common-anode LEDs; these outputs are not logic-level GPIO.
Drives the common anode of digit 4.
Connect to the common anode of display digit 4.
Use common-anode LEDs; these outputs are not logic-level GPIO.
Drives the common anode of digit 3.
Connect to the common anode of display digit 3.
Use common-anode LEDs; these outputs are not logic-level GPIO.
Drives the common anode of digit 2.
Connect to the common anode of display digit 2.
Use common-anode LEDs; these outputs are not logic-level GPIO.
Drives the common anode of digit 1.
Connect to the common anode of display digit 1.
Use common-anode LEDs; these outputs are not logic-level GPIO.
Powers the logic and display drivers.
The example uses a regulated 5 V rail with 100 nF and 100 µF bypass near the IC.
Electrical and timing characteristics are specified at 4.5–5.5 V; follow the purchased part revision.
Transfers command, display and key bytes; the IC pulls this line LOW for acknowledgement.
Use a 10 kΩ pull-up to 5 V and an open-drain or releasable host pin.
Release the line for the ninth ACK clock and when reading keys; never contend with the IC output.
Clocks data on rising edges.
Use a 10 kΩ pull-up to 5 V; the example host clocks at 100 kHz.
This two-wire protocol is not I²C: no slave address, and bytes are sent least-significant bit first.
First row input for the 8 × 2 key matrix.
Optional keys connect to the SEG/KS scan lines as shown in the manufacturer circuit.
Internal nominal 10 kΩ pull-down; leave unused key inputs unconnected.
Second row input for the 8 × 2 key matrix.
Read with command 0x42; one key code is returned.
Combined key presses are not supported; idle key data is 0xFF.