LM319 Specifications
Review LM319 electrical specifications, operating conditions and package details.
Key specifications
The output transistor pulls LOW or releases the line. A separate external resistor creates HIGH; the IC does not actively source that state.
Package details
LM319N/NOPB · PDIP-14
| Property | Details |
|---|---|
| Manufacturer | Texas Instruments |
| Part number | LM319N/NOPB |
| Package | PDIP-14 |
| Connections | 14 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | dip |
| Thermal reference | Board and package dependent; see manufacturer data |
Supply and input conditions
Selected TI LM319, not the A-grade column
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply capability | Single 5 V through ±15 V | Electrical-section applicability; observe all ground-relative limits |
| Illustrated rails | V+ = 5 V; V− = 0 V | Pin 11 positive; pin 6 negative |
| Input range at 5 V | 1–3 V | Ground is outside the specified input range |
| Input range at ±15 V | ±13 V typical | Manufacturer electrical table |
| Ambient operating range | 0–70°C | LM319N/M commercial orders |
| Ground-to-supply operating note | Do not exceed 16 V | Manufacturer electrical-section instruction |
No specifications match. Try a parameter name or a unit.
Recommended operating conditions and absolute stress limits are distinct.
Input accuracy and current
±15 V; 25°C unless noted
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Input offset | 2 mV typical; 8 mV maximum | RS ≤ 5 kΩ |
| Offset over temperature | 10 mV maximum | 0–70°C; RS ≤ 5 kΩ |
| Input bias current | 250 nA typical; 1000 nA maximum | 1200 nA maximum over temperature |
| Input offset current | 80 nA typical; 200 nA maximum | 300 nA maximum over temperature |
| Voltage gain | 8 V/mV minimum; 40 V/mV typical | Output pulled to 15 V through 1.4 kΩ |
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Offset specifications use the manufacturer output/load definition; do not treat typical values as guarantees.
Response and open-collector output
Retain the test conditions
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Response time | 80 ns typical | ±15 V; 100 mV step with 5 mV overdrive |
| Saturation at 25 mA | 0.75 V typical; 1.5 V maximum | VIN differential ≤ −10 mV; 25°C |
| Saturation at ≤3.2 mA | 0.3 V typical; 0.4 V maximum | V+ ≥ 4.5 V, V− = 0 V; differential ≤ −10 mV |
| Output leakage | 0.2 µA typical; 10 µA maximum | 35 V output, 25°C; V− and GND = 0 V; differential ≥ 10 mV |
| Pull-up rise time | Depends on resistance and capacitance | Do not equate the 80 ns figure with every circuit edge |
No specifications match. Try a parameter name or a unit.
A 10 kΩ pull-up is suitable for this low-current DC illustration, not a promise of maximum switching speed.
Power and stress limits
Check every voltage reference
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Positive supply current at 5 V | 4.3 mA typical | 25°C; V− = 0 V |
| Positive supply current at ±15 V | 8 mA typical; 12.5 mA maximum | 25°C |
| Negative supply current at ±15 V | 3 mA typical; 5 mA maximum | 25°C |
| Absolute total supply | 36 V | Stress limit |
| Absolute differential input | ±5 V | Do not apply supply-span differential signals |
| Absolute output to V− | 36 V | Collector stress limit |
| Absolute GND to V− / V+ | 25 V / 18 V | Separate output-stage return constraints |
| Absolute power dissipation | 500 mW | Thermal conditions and derating still apply |
No specifications match. Try a parameter name or a unit.
Absolute limits do not authorize continuous operation at those conditions.
A 2 V threshold detector
Calculated DC example, not a timing simulation
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Reference divider | 30 kΩ upper; 20 kΩ lower | 5 × 20/(30+20) = 2.00 V, before input-current error |
| VIN = 1.50 V | OUT1 LOW | Input 4 below reference input 5 |
| VIN = 2.50 V | OUT1 released / HIGH | External pull-up creates high level |
| Pull-up | 10 kΩ to +5 V | Connected to output pin 12 |
| Illustrative LOW current | About 0.47 mA | (5−0.3)/10 kΩ; 0.3 V is a typical estimate |
| Second comparator | IN+9 = VIN; IN−10 = VREF | Output 7 left unused |
| Local bypass | 100 nF between pins 11 and 6 | All GND symbols in this example share 0 V |
No specifications match. Try a parameter name or a unit.
Input bias loads the divider; use a lower source impedance or buffer when threshold accuracy matters.
Fourteen-pin package map
LM319N/NOPB · PDIP-14
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Lead pitch | 2.54 mm | Through-hole |
| Channel 1 | 4 IN+; 5 IN−; 12 OUT | Output-stage return: pin 3 |
| Channel 2 | 9 IN+; 10 IN−; 7 OUT | Output-stage return: pin 8 |
| Analog supplies | 11 V+; 6 V− | Shared by both channels |
| No connection | 1, 2, 13, 14 | Leave open |
| Pin-map source | TI fourteen-pin drawing, page 3 | Cross-checked against ST fourteen-pin drawing |
| Layout | Short bypass and output-current loops | Keep output switching currents away from input/reference traces |
No specifications match. Try a parameter name or a unit.
Use the package drawing: the TI pin-function table has inconsistent ten/fourteen-pin column labels.
Connections by function
Select a pin for its function, connection guidance and electrical notes.