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High-speed dual voltage comparator

LM319 Specifications

Review LM319 electrical specifications, operating conditions and package details.

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Key specifications

The output transistor pulls LOW or releases the line. A separate external resistor creates HIGH; the IC does not actively source that state.

Independent comparators2 Separate output-stage returns
Typical response80 ns · ±15 V test
Illustrated supply5 V · inputs kept at 1–3 V
Selected ambient range0–70 °C

Operating profile

Supply, signals and operating conditions

LM319 operating profile
ParameterValueConditions / notes
Selected packagePDIP-14LM319N/NOPB
Reference threshold2.00V · 30 kΩ / 20 kΩ divider
Output topologyOpen collector10 kΩ external pull-up in example
Use these values with the stated grade and test conditions.

Package details

LM319N/NOPB · PDIP-14

Selected package
Selected LM319 physical package
PropertyDetails
ManufacturerTexas Instruments
Part numberLM319N/NOPB
PackagePDIP-14
Connections14 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codedip
Thermal referenceBoard and package dependent; see manufacturer data

Supply and input conditions

Selected TI LM319, not the A-grade column

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ParameterValueConditions / notes
Supply capabilitySingle 5 V through ±15 VElectrical-section applicability; observe all ground-relative limits
Illustrated railsV+ = 5 V; V− = 0 VPin 11 positive; pin 6 negative
Input range at 5 V1–3 VGround is outside the specified input range
Input range at ±15 V±13 V typicalManufacturer electrical table
Ambient operating range0–70°CLM319N/M commercial orders
Ground-to-supply operating noteDo not exceed 16 VManufacturer electrical-section instruction

Recommended operating conditions and absolute stress limits are distinct.

Input accuracy and current

±15 V; 25°C unless noted

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ParameterValueConditions / notes
Input offset2 mV typical; 8 mV maximumRS ≤ 5 kΩ
Offset over temperature10 mV maximum0–70°C; RS ≤ 5 kΩ
Input bias current250 nA typical; 1000 nA maximum1200 nA maximum over temperature
Input offset current80 nA typical; 200 nA maximum300 nA maximum over temperature
Voltage gain8 V/mV minimum; 40 V/mV typicalOutput pulled to 15 V through 1.4 kΩ

Offset specifications use the manufacturer output/load definition; do not treat typical values as guarantees.

Response and open-collector output

Retain the test conditions

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ParameterValueConditions / notes
Response time80 ns typical±15 V; 100 mV step with 5 mV overdrive
Saturation at 25 mA0.75 V typical; 1.5 V maximumVIN differential ≤ −10 mV; 25°C
Saturation at ≤3.2 mA0.3 V typical; 0.4 V maximumV+ ≥ 4.5 V, V− = 0 V; differential ≤ −10 mV
Output leakage0.2 µA typical; 10 µA maximum35 V output, 25°C; V− and GND = 0 V; differential ≥ 10 mV
Pull-up rise timeDepends on resistance and capacitanceDo not equate the 80 ns figure with every circuit edge

A 10 kΩ pull-up is suitable for this low-current DC illustration, not a promise of maximum switching speed.

Power and stress limits

Check every voltage reference

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ParameterValueConditions / notes
Positive supply current at 5 V4.3 mA typical25°C; V− = 0 V
Positive supply current at ±15 V8 mA typical; 12.5 mA maximum25°C
Negative supply current at ±15 V3 mA typical; 5 mA maximum25°C
Absolute total supply36 VStress limit
Absolute differential input±5 VDo not apply supply-span differential signals
Absolute output to V−36 VCollector stress limit
Absolute GND to V− / V+25 V / 18 VSeparate output-stage return constraints
Absolute power dissipation500 mWThermal conditions and derating still apply

Absolute limits do not authorize continuous operation at those conditions.

A 2 V threshold detector

Calculated DC example, not a timing simulation

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ParameterValueConditions / notes
Reference divider30 kΩ upper; 20 kΩ lower5 × 20/(30+20) = 2.00 V, before input-current error
VIN = 1.50 VOUT1 LOWInput 4 below reference input 5
VIN = 2.50 VOUT1 released / HIGHExternal pull-up creates high level
Pull-up10 kΩ to +5 VConnected to output pin 12
Illustrative LOW currentAbout 0.47 mA(5−0.3)/10 kΩ; 0.3 V is a typical estimate
Second comparatorIN+9 = VIN; IN−10 = VREFOutput 7 left unused
Local bypass100 nF between pins 11 and 6All GND symbols in this example share 0 V

Input bias loads the divider; use a lower source impedance or buffer when threshold accuracy matters.

Fourteen-pin package map

LM319N/NOPB · PDIP-14

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ParameterValueConditions / notes
Lead pitch2.54 mmThrough-hole
Channel 14 IN+; 5 IN−; 12 OUTOutput-stage return: pin 3
Channel 29 IN+; 10 IN−; 7 OUTOutput-stage return: pin 8
Analog supplies11 V+; 6 V−Shared by both channels
No connection1, 2, 13, 14Leave open
Pin-map sourceTI fourteen-pin drawing, page 3Cross-checked against ST fourteen-pin drawing
LayoutShort bypass and output-current loopsKeep output switching currents away from input/reference traces

Use the package drawing: the TI pin-function table has inconsistent ten/fourteen-pin column labels.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Not connected4 pins

Supply4 pins

Comparator inputs4 pins

Open collectors2 pins

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

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