MAX485 Reference Tables, Pins & Specifications

Pin reference

Signal names, electrical functions and connection guidance

PDIP-8

Physical pin numbers8 pins

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MAX485 pin functions and connections
Signal	Type	Function & connection
RO	Receiver data output	When enabled, HIGH for A − B ≥ 200 mV and LOW for A − B ≤ −200 mV. High impedance when RE̅ is HIGH. Connection guidance Connect to a 5 V-compatible controller RX input. Open receiver inputs produce HIGH; a terminated idle bus needs separately designed bias.
RE̅	Active-LOW receiver enable	LOW enables RO; HIGH releases RO to high impedance. Connection guidance Join DE for one direction signal: LOW receive, HIGH transmit.
DE	Active-HIGH driver enable	HIGH enables differential driver outputs; LOW releases the bus. Connection guidance Drive from the direction GPIO; add a 10 kΩ pull-down for a receive-first startup.
DI	Driver data input	With DE HIGH, DI HIGH makes A higher than B. DI LOW reverses the polarity. Connection guidance Connect to controller UART TX. Logic HIGH ≥ 2.0 V; LOW ≤ 0.8 V.
GND	Supply and signal reference	Reference for logic levels and bus common-mode voltage. Connection guidance Join the controller ground and the intended bus reference conductor.
A	Non-inverting bus terminal	Non-inverting driver output and receiver input. Connection guidance Connect A to A on the other node using a twisted pair. Receiver common-mode operating range −7 to +12 V.
B	Inverting bus terminal	Inverting driver output and receiver input. Connection guidance Connect B to B on the other node; verify vendor naming at third-party terminals.
VCC	Regulated supply	Powers the transceiver from a nominal 5 V rail. Connection guidance Use 4.75–5.25 V and 100 nF directly to pin 5. This is the 5 V MAX485, not a 3.3 V MAX3485.

Driver and receiver truth states

Controls are independent

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
DE HIGH; DI HIGH	A HIGH relative to B	Transmitter enabled
DE HIGH; DI LOW	A LOW relative to B	Transmitter enabled
DE LOW	A and B driver outputs high impedance	Receiver may remain enabled
RE̅ LOW; A − B ≥ +200 mV	RO HIGH	Within common-mode range
RE̅ LOW; A − B ≤ −200 mV	RO LOW	Within common-mode range
RE̅ HIGH	RO high impedance	External input may need a defined idle state
RE̅ LOW; both bus inputs open	RO HIGH	Specified open-input fail-safe
DE LOW; RE̅ HIGH	Driver and receiver disabled	MAX485 has no low-current shutdown mode

Do not assume a terminated, unbiased idle bus has the same fail-safe behavior as physically open receiver inputs.

Supply, logic and receiver

Selected industrial grades

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
Supply voltage	4.75–5.25 V	Nominal 5 V
Ambient range	−40 to +85°C	EPA / ESA orderables
Logic input HIGH / LOW	≥ 2.0 V / ≤ 0.8 V	DI, DE and RE̅
RO HIGH / LOW	≥ 3.5 V / ≤ 0.4 V	Source / sink 4 mA
Receiver common-mode	−7 to +12 V	Referenced to local GND
Receiver threshold region	−200 to +200 mV	No guaranteed level inside the transition region
Typical input hysteresis	70 mV	Common-mode 0 V
Receiver input resistance	12 kΩ minimum	One standard unit load

A 3.3 V controller may drive the logic inputs, but its RX input must tolerate or translate the 5 V RO level.

Driver and power characteristics

Manufacturer specified test loads

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Loaded differential output	1.5 V minimum	RS-485 test load: two 27 Ω branches
No-load current, DE LOW	300 µA typical; 500 µA maximum	MAX485; defined input levels
No-load current, DE HIGH	500 µA typical; 900 µA maximum	MAX485; driver enabled and unloaded
Receiver bus loading	Up to 32 standard unit loads	Bias, cable and other loads also matter
Driver protection	Current limiting and thermal shutdown	Not permission for continuous bus contention
Slew-rate limiting	Not provided	Use controlled cable topology
Low-power shutdown	Not provided in MAX485	MAX481 / 483 / 487 have different features

The MAX487 and MAX1487 quarter-unit-load and 128-node figures do not apply to MAX485.

Data path and bus timing

5 V ±5% · manufacturer test circuits

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Maximum data rate	2.5 Mbit/s	Do not infer this rate over every cable length
Bit period at 2.5 Mbit/s	400 ns	1 / data rate
Driver propagation	10–60 ns; 30 ns typical	54 Ω differential load; 100 pF each output
Driver rise / fall	3–40 ns; 15 ns typical	Specified test load
Receiver propagation	200 ns maximum; 90 ns typical	15 pF output load
Driver enable / disable	70 ns maximum; 40 ns typical	Specified test circuits
Receiver enable / disable	50 ns maximum; 20 ns typical	Specified test circuits

Protocol turnaround must also include UART completion, firmware latency, cable delay and the receiving node’s timing.

Two-node half-duplex connection

5 V controllers · short teaching link

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
UART TX / RX	TX → DI4; RO1 → RX	5 V-compatible logic
Direction	GPIO → DE3 and RE̅2	10 kΩ pull-down: default receive
Twisted pair	A6 → A6; B7 → B7	Keep stubs short
Cable-end termination	120 Ω across A–B at each end	Two total; not at every node
Single idle-bias location	390 Ω from +5 V to A; 390 Ω from B to GND	Example only; review loading and tolerances
Ideal idle difference	5 × 60 / (390 + 60 + 390) ≈ 0.357 V	Two 120 Ω terminators in parallel; receiver loads omitted
Supply bypass	100 nF at each IC, VCC8 to GND5	Short local paths
Signal reference	Common reference conductor	Maintain each receiver’s common-mode limits

The bias estimate is a design illustration. Recalculate for actual transceiver count, tolerances, cable and ground offsets.

Packages and stress limits

MAX485EPA+ · PDIP-8

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
PDIP-8 EPA	P8-1 · 2.54 mm pitch	7.62 mm nominal lead rows
Narrow SOIC-8 ESA	S8-2 · 1.27 mm pitch	Separate surface-mount footprint
Supply absolute maximum	12 V	Not the normal operating voltage
A / B absolute voltage	−8 to +12.5 V	Receiver operation remains −7 to +12 V common mode
Logic pin stress	−0.5 to VCC + 0.5 V	DI, enables and RO
PDIP dissipation at 70°C	727 mW	Derate 9.09 mW/°C above 70°C
SOIC dissipation at 70°C	471 mW	Derate 5.88 mW/°C above 70°C
Storage temperature	−65 to +160°C	Unpowered

The alternate µMAX package in this family uses a different pin arrangement and is not represented by these DIP/SO maps.