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5 V half-duplex RS-485 transceiver

MAX485 Specifications

Review MAX485 electrical specifications, operating conditions and package details.

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Key specifications

A differential driver converts DI into opposite bus voltages. A receiver compares A with B and recovers a logic level. Separate enable controls determine who is driving and listening.

Operating supply4.75–5.25 V
Maximum data rate2.5 Mbit/s
Selected E grades−40–85 °C
CommunicationHalf duplex One active driver at a time

Operating profile

Supply, signals and operating conditions

MAX485 operating profile
ParameterValueConditions / notes
Selected packagePDIP-8MAX485EPA+
Receiver loading1 unit load12 kΩ minimum · 32 standard loads
Joined DE / RE̅LOW = receiveHIGH = transmit
Use these values with the stated grade and test conditions.

Package details

MAX485EPA+ · PDIP-8

Selected package
Selected MAX485 physical package
PropertyDetails
ManufacturerAnalog Devices / Maxim
Part numberMAX485EPA+
PackagePDIP-8
Connections8 pins
MountingThrough-hole
Lead pitch2.54 mm
Package codedip
Thermal referenceBoard and package dependent; see manufacturer data

Driver and receiver truth states

Controls are independent

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ParameterValueConditions / notes
DE HIGH; DI HIGHA HIGH relative to BTransmitter enabled
DE HIGH; DI LOWA LOW relative to BTransmitter enabled
DE LOWA and B driver outputs high impedanceReceiver may remain enabled
RE̅ LOW; A − B ≥ +200 mVRO HIGHWithin common-mode range
RE̅ LOW; A − B ≤ −200 mVRO LOWWithin common-mode range
RE̅ HIGHRO high impedanceExternal input may need a defined idle state
RE̅ LOW; both bus inputs openRO HIGHSpecified open-input fail-safe
DE LOW; RE̅ HIGHDriver and receiver disabledMAX485 has no low-current shutdown mode

Do not assume a terminated, unbiased idle bus has the same fail-safe behavior as physically open receiver inputs.

Supply, logic and receiver

Selected industrial grades

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ParameterValueConditions / notes
Supply voltage4.75–5.25 VNominal 5 V
Ambient range−40 to +85°CEPA / ESA orderables
Logic input HIGH / LOW≥ 2.0 V / ≤ 0.8 VDI, DE and RE̅
RO HIGH / LOW≥ 3.5 V / ≤ 0.4 VSource / sink 4 mA
Receiver common-mode−7 to +12 VReferenced to local GND
Receiver threshold region−200 to +200 mVNo guaranteed level inside the transition region
Typical input hysteresis70 mVCommon-mode 0 V
Receiver input resistance12 kΩ minimumOne standard unit load

A 3.3 V controller may drive the logic inputs, but its RX input must tolerate or translate the 5 V RO level.

Driver and power characteristics

Manufacturer specified test loads

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ParameterValueConditions / notes
Loaded differential output1.5 V minimumRS-485 test load: two 27 Ω branches
No-load current, DE LOW300 µA typical; 500 µA maximumMAX485; defined input levels
No-load current, DE HIGH500 µA typical; 900 µA maximumMAX485; driver enabled and unloaded
Receiver bus loadingUp to 32 standard unit loadsBias, cable and other loads also matter
Driver protectionCurrent limiting and thermal shutdownNot permission for continuous bus contention
Slew-rate limitingNot providedUse controlled cable topology
Low-power shutdownNot provided in MAX485MAX481 / 483 / 487 have different features

The MAX487 and MAX1487 quarter-unit-load and 128-node figures do not apply to MAX485.

Data path and bus timing

5 V ±5% · manufacturer test circuits

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ParameterValueConditions / notes
Maximum data rate2.5 Mbit/sDo not infer this rate over every cable length
Bit period at 2.5 Mbit/s400 ns1 / data rate
Driver propagation10–60 ns; 30 ns typical54 Ω differential load; 100 pF each output
Driver rise / fall3–40 ns; 15 ns typicalSpecified test load
Receiver propagation200 ns maximum; 90 ns typical15 pF output load
Driver enable / disable70 ns maximum; 40 ns typicalSpecified test circuits
Receiver enable / disable50 ns maximum; 20 ns typicalSpecified test circuits

Protocol turnaround must also include UART completion, firmware latency, cable delay and the receiving node’s timing.

Two-node half-duplex connection

5 V controllers · short teaching link

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ParameterValueConditions / notes
UART TX / RXTX → DI4; RO1 → RX5 V-compatible logic
DirectionGPIO → DE3 and RE̅210 kΩ pull-down: default receive
Twisted pairA6 → A6; B7 → B7Keep stubs short
Cable-end termination120 Ω across A–B at each endTwo total; not at every node
Single idle-bias location390 Ω from +5 V to A; 390 Ω from B to GNDExample only; review loading and tolerances
Ideal idle difference5 × 60 / (390 + 60 + 390) ≈ 0.357 VTwo 120 Ω terminators in parallel; receiver loads omitted
Supply bypass100 nF at each IC, VCC8 to GND5Short local paths
Signal referenceCommon reference conductorMaintain each receiver’s common-mode limits

The bias estimate is a design illustration. Recalculate for actual transceiver count, tolerances, cable and ground offsets.

Packages and stress limits

MAX485EPA+ · PDIP-8

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ParameterValueConditions / notes
PDIP-8 EPAP8-1 · 2.54 mm pitch7.62 mm nominal lead rows
Narrow SOIC-8 ESAS8-2 · 1.27 mm pitchSeparate surface-mount footprint
Supply absolute maximum12 VNot the normal operating voltage
A / B absolute voltage−8 to +12.5 VReceiver operation remains −7 to +12 V common mode
Logic pin stress−0.5 to VCC + 0.5 VDI, enables and RO
PDIP dissipation at 70°C727 mWDerate 9.09 mW/°C above 70°C
SOIC dissipation at 70°C471 mWDerate 5.88 mW/°C above 70°C
Storage temperature−65 to +160°CUnpowered

The alternate µMAX package in this family uses a different pin arrangement and is not represented by these DIP/SO maps.

Connections by function

Select a pin for its function, connection guidance and electrical notes.

Receive data1 pin

Direction controls2 pins

Transmit data1 pin

Ground1 pin

Differential bus2 pins

Supply1 pin

Read the conditions with every value

Typical values describe stated test conditions. Absolute maximum ratings are stress limits, not operating targets.

Official PDF datasheet

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