MAX485 Specifications
Review MAX485 electrical specifications, operating conditions and package details.
Key specifications
A differential driver converts DI into opposite bus voltages. A receiver compares A with B and recovers a logic level. Separate enable controls determine who is driving and listening.
Package details
MAX485EPA+ · PDIP-8
| Property | Details |
|---|---|
| Manufacturer | Analog Devices / Maxim |
| Part number | MAX485EPA+ |
| Package | PDIP-8 |
| Connections | 8 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | dip |
| Thermal reference | Board and package dependent; see manufacturer data |
Driver and receiver truth states
Controls are independent
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| Parameter | Value | Conditions / notes |
|---|---|---|
| DE HIGH; DI HIGH | A HIGH relative to B | Transmitter enabled |
| DE HIGH; DI LOW | A LOW relative to B | Transmitter enabled |
| DE LOW | A and B driver outputs high impedance | Receiver may remain enabled |
| RE̅ LOW; A − B ≥ +200 mV | RO HIGH | Within common-mode range |
| RE̅ LOW; A − B ≤ −200 mV | RO LOW | Within common-mode range |
| RE̅ HIGH | RO high impedance | External input may need a defined idle state |
| RE̅ LOW; both bus inputs open | RO HIGH | Specified open-input fail-safe |
| DE LOW; RE̅ HIGH | Driver and receiver disabled | MAX485 has no low-current shutdown mode |
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Do not assume a terminated, unbiased idle bus has the same fail-safe behavior as physically open receiver inputs.
Supply, logic and receiver
Selected industrial grades
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply voltage | 4.75–5.25 V | Nominal 5 V |
| Ambient range | −40 to +85°C | EPA / ESA orderables |
| Logic input HIGH / LOW | ≥ 2.0 V / ≤ 0.8 V | DI, DE and RE̅ |
| RO HIGH / LOW | ≥ 3.5 V / ≤ 0.4 V | Source / sink 4 mA |
| Receiver common-mode | −7 to +12 V | Referenced to local GND |
| Receiver threshold region | −200 to +200 mV | No guaranteed level inside the transition region |
| Typical input hysteresis | 70 mV | Common-mode 0 V |
| Receiver input resistance | 12 kΩ minimum | One standard unit load |
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A 3.3 V controller may drive the logic inputs, but its RX input must tolerate or translate the 5 V RO level.
Driver and power characteristics
Manufacturer specified test loads
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Loaded differential output | 1.5 V minimum | RS-485 test load: two 27 Ω branches |
| No-load current, DE LOW | 300 µA typical; 500 µA maximum | MAX485; defined input levels |
| No-load current, DE HIGH | 500 µA typical; 900 µA maximum | MAX485; driver enabled and unloaded |
| Receiver bus loading | Up to 32 standard unit loads | Bias, cable and other loads also matter |
| Driver protection | Current limiting and thermal shutdown | Not permission for continuous bus contention |
| Slew-rate limiting | Not provided | Use controlled cable topology |
| Low-power shutdown | Not provided in MAX485 | MAX481 / 483 / 487 have different features |
No specifications match. Try a parameter name or a unit.
The MAX487 and MAX1487 quarter-unit-load and 128-node figures do not apply to MAX485.
Data path and bus timing
5 V ±5% · manufacturer test circuits
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Maximum data rate | 2.5 Mbit/s | Do not infer this rate over every cable length |
| Bit period at 2.5 Mbit/s | 400 ns | 1 / data rate |
| Driver propagation | 10–60 ns; 30 ns typical | 54 Ω differential load; 100 pF each output |
| Driver rise / fall | 3–40 ns; 15 ns typical | Specified test load |
| Receiver propagation | 200 ns maximum; 90 ns typical | 15 pF output load |
| Driver enable / disable | 70 ns maximum; 40 ns typical | Specified test circuits |
| Receiver enable / disable | 50 ns maximum; 20 ns typical | Specified test circuits |
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Protocol turnaround must also include UART completion, firmware latency, cable delay and the receiving node’s timing.
Two-node half-duplex connection
5 V controllers · short teaching link
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| Parameter | Value | Conditions / notes |
|---|---|---|
| UART TX / RX | TX → DI4; RO1 → RX | 5 V-compatible logic |
| Direction | GPIO → DE3 and RE̅2 | 10 kΩ pull-down: default receive |
| Twisted pair | A6 → A6; B7 → B7 | Keep stubs short |
| Cable-end termination | 120 Ω across A–B at each end | Two total; not at every node |
| Single idle-bias location | 390 Ω from +5 V to A; 390 Ω from B to GND | Example only; review loading and tolerances |
| Ideal idle difference | 5 × 60 / (390 + 60 + 390) ≈ 0.357 V | Two 120 Ω terminators in parallel; receiver loads omitted |
| Supply bypass | 100 nF at each IC, VCC8 to GND5 | Short local paths |
| Signal reference | Common reference conductor | Maintain each receiver’s common-mode limits |
No specifications match. Try a parameter name or a unit.
The bias estimate is a design illustration. Recalculate for actual transceiver count, tolerances, cable and ground offsets.
Packages and stress limits
MAX485EPA+ · PDIP-8
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| Parameter | Value | Conditions / notes |
|---|---|---|
| PDIP-8 EPA | P8-1 · 2.54 mm pitch | 7.62 mm nominal lead rows |
| Narrow SOIC-8 ESA | S8-2 · 1.27 mm pitch | Separate surface-mount footprint |
| Supply absolute maximum | 12 V | Not the normal operating voltage |
| A / B absolute voltage | −8 to +12.5 V | Receiver operation remains −7 to +12 V common mode |
| Logic pin stress | −0.5 to VCC + 0.5 V | DI, enables and RO |
| PDIP dissipation at 70°C | 727 mW | Derate 9.09 mW/°C above 70°C |
| SOIC dissipation at 70°C | 471 mW | Derate 5.88 mW/°C above 70°C |
| Storage temperature | −65 to +160°C | Unpowered |
No specifications match. Try a parameter name or a unit.
The alternate µMAX package in this family uses a different pin arrangement and is not represented by these DIP/SO maps.
Connections by function
Select a pin for its function, connection guidance and electrical notes.