MCP2515 Reference Tables, Pins & Specifications | The Engineering Projects

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Selected packagePDIP-18MCP2515-I/P

Physical connections18 pinsPackage-specific numbering

Reference collection8 tables53 parameters & pin functions

Pin reference

Signal names, electrical functions and connection guidance

PDIP-18

Physical pin numbers18 pins

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MCP2515 pin functions and connections
Pin	Signal	Type	Function & connection
	TXCAN	Logic transmit output	Sends the CAN protocol engine’s dominant/recessive logic to a transceiver. Connection guidance Connect to MCP2562 TXD pin 1. This is not CANH or CANL; never connect directly to the cable.
	RXCAN	Logic receive input	Receives the bus state from the external transceiver. Connection guidance Connect to MCP2562 RXD pin 4.
	CLKOUT/SOF	Clock or start-of-frame output	Outputs a divided oscillator clock or a selected start-of-frame indication. Connection guidance Leave open when unused. After reset the enabled clock defaults to FOSC / 8.
	TX0RTS̅	Request-to-send input	Active-LOW request for transmit buffer 0, or a general-purpose input according to TXRTSCTRL. Connection guidance Leave unconnected when unused; its internal pull-up holds it HIGH. Approximately 100 kΩ internal pull-up to VDD.
	TX1RTS̅	Request-to-send input	Active-LOW request for transmit buffer 1, or a general-purpose input according to TXRTSCTRL. Connection guidance Leave unconnected when unused; its internal pull-up holds it HIGH. Approximately 100 kΩ internal pull-up to VDD.
	TX2RTS̅	Request-to-send input	Active-LOW request for transmit buffer 2, or a general-purpose input according to TXRTSCTRL. Connection guidance Leave unconnected when unused; its internal pull-up holds it HIGH. Approximately 100 kΩ internal pull-up to VDD.
	OSC2	Oscillator output	Feedback terminal for crystal/resonator operation. Connection guidance Leave open in the external-clock example.
	OSC1	Oscillator / clock input	Accepts the clock used for CAN bit timing and internal operation. Connection guidance Apply a 20 MHz, 0–5 V oscillator output with 45–55% duty cycle.
	VSS	Ground return	Ground for logic, clock and I/O. Connection guidance Join the controller, oscillator and transceiver reference.
	RX1BF̅	Receive-buffer 1 flag	Configurable buffer-full indication or general-purpose output. Connection guidance Leave open when using INT alone.
	RX0BF̅	Receive-buffer 0 flag	Configurable buffer-full indication or general-purpose output. Connection guidance Leave open when using INT alone.
	INT̅	Active-LOW interrupt	Signals enabled interrupt conditions; software must inspect and service their flags. Connection guidance Connect to a compatible controller interrupt input.
	SCK	SPI clock input	Clocks commands and register data; SPI modes 0 and 3 are supported. Connection guidance Connect controller SCK; use 1 MHz for the example.
	SI	SPI data input	Receives instruction, address and data from the controller. Connection guidance Connect MOSI.
	SO	SPI data output	Returns register and buffer data; high impedance when CS is HIGH. Connection guidance Connect MISO.
	CS̅	Active-LOW chip select	LOW starts an SPI instruction; return HIGH before the next instruction. Connection guidance Connect a dedicated controller select and 10 kΩ pull-up to +5 V.
	RESET̅	Active-LOW reset	Initializes registers and enters Configuration mode. Connection guidance Use a 10 kΩ pull-up and controller reset output; hold LOW at least 2 µs. Allow oscillator startup before SPI access.
	VDD	Positive supply	Powers the CAN controller and its I/O. Connection guidance Use +5 V with 100 nF directly to VSS9. Operating range 2.7–5.5 V; logic thresholds scale with supply.

Protocol and storage

Classical CAN 2.0B

Manufacturer-referenced values7 parameters

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Parameter	Value	Conditions / notes
Bus rate	Up to 1 Mbit/s	Subject to oscillator and network timing
Identifiers	11-bit standard / 29-bit extended	Data and remote frames
Data field	0–8 bytes	No CAN FD or bit-rate switching
Transmit storage	Three prioritized buffers	Abort and one-shot options
Receive storage	Two buffers	Priority and optional rollover
Acceptance	Six filters and two masks	Configure before Normal mode
External line interface	Required CAN transceiver	TXCAN / RXCAN are logic signals

A controller and a transceiver solve different parts of the CAN interface.

Useful SPI instructions

Most significant bit first · separate CS cycle per command

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
RESET	0xC0	Initialize and enter Configuration mode
READ	0x03, address, dummy clocks	Consecutive register bytes may follow
WRITE	0x02, address, data…	Sequential register write
BIT MODIFY	0x05, address, mask, data	Only supported registers; mask 1 permits change
READ STATUS	0xA0	Frequently used RX/TX status
RX STATUS	0xB0	Received-frame type and matching filter
RTS buffer 0	0x81	Request already-loaded TXB0 transmission
SPI timing	10 MHz maximum; 50 ns CS setup/hold	Modes 0 and 3

The controller expects an instruction immediately after CS falls. Raise CS before issuing another instruction.

Operating modes

Request via CANCTRL; confirm via CANSTAT

Manufacturer-referenced values6 parameters

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Parameter	Value	Conditions / notes
Configuration	REQOP 100	Required for bit timing, filters, masks and TXRTSCTRL
Normal	REQOP 000	Transmit, receive and acknowledge CAN frames
Sleep	REQOP 001	Oscillator stopped; wake-up conditions apply
Loopback	REQOP 010	Internal communications test without bus transmission
Listen-only	REQOP 011	Observe bus without transmitting or acknowledging
Mode confirmation	Read OPMOD bits	A request may wait for pending transmissions

Listen-only nodes do not supply the acknowledgment required for a transmitting node’s normal successful frame.

125 kbit/s configuration example

20 MHz external clock · single sample

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
Oscillator period	50 ns	1 / 20 MHz
BRP register field	4	TQ = 2 × (BRP + 1) / FOSC
Time quantum	500 ns	Prescaler division by 10
Segments	Sync 1; Prop 2; PS1 7; PS2 6	16 TQ per bit
Sample point	(1 + 2 + 7) / 16 = 62.5%	At the end of Phase Segment 1
Synchronization jump width	1 TQ	Must not exceed PS2
CNF1 / CNF2 / CNF3	0x04 / 0xB1 / 0x05	BTLMODE=1, SAM=0; wake filter/SOF disabled
Result	16 × 500 ns = 8 µs per bit	125000 bits/s

This is the manufacturer’s illustrative timing split, not a universal network prescription. Review propagation, oscillator tolerance and the other nodes.

Supply, clock and logic

MCP2515-I/P and MCP2515-I/SO

Manufacturer-referenced values10 parameters

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Parameter	Value	Conditions / notes
Operating supply / temperature	2.7–5.5 V / −40 to +85°C	I grade
SPI input HIGH	≥ 0.7 × VDD	SCK, SI and CS
SPI input LOW	≤ 0.4 × VDD	SCK, SI and CS
RXCAN HIGH / LOW	≥ 2.0 V / ≤ 0.15 × VDD	Different input thresholds from SPI
Reset HIGH / LOW	≥ 0.85 × VDD / ≤ 0.15 × VDD	Schmitt reset input
External clock range	1–25 MHz over 2.7–5.5 V	Up to 40 MHz at 4.5–5.5 V
Clock duty cycle	45–55%	External clock input
Active current	10 mA maximum	5.5 V, oscillator25 MHz, SPI1 MHz, SO open
Sleep current, I grade	5 µA maximum	Defined inputs and CS / TXnRTS HIGH
Hardware reset LOW	2 µs minimum	Then allow 128 oscillator cycles for startup

At 5 V, a 3.3 V HIGH does not meet the SPI 0.7 VDD threshold. Use compatible levels or translation.

Controller-to-CAN connection

5 V logic · 20 MHz · 125 kbit/s

Manufacturer-referenced values8 parameters

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Parameter	Value	Conditions / notes
Host SPI	SCK13, MOSI→SI14, SO15→MISO, CS16	Start with mode0 at1 MHz
Host control	INT12→interrupt; RESET17→reset output	10 kΩ pull-ups on CS and RESET
External oscillator	20 MHz output→OSC1 pin8	OSC2 pin7 open; oscillator bypass per its data
CAN controller/transceiver	TXCAN1→MCP2562 TXD1; RXD4→RXCAN2	Logic connections, not bus pins
MCP2562 supplies	VDD3 and VIO5 to5 V; VSS2 GND	100 nF local supply bypass; STBY8 LOW
Bus	MCP2562 CANH7 and CANL6	Twisted pair; two120 Ω end terminators
Unused outputs	CLKOUT3, RX1BF10, RX0BF11 open	Unused TXnRTS inputs have internal pull-ups
Firmware	Reset, configure timing and filters, enter Normal mode	Another matching normal node must acknowledge

All ground references are common in this teaching circuit. Protection, isolation and cable length require a system-specific design.

Packages and stress limits

MCP2515-I/P · PDIP-18

Manufacturer-referenced values6 parameters

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Parameter	Value	Conditions / notes
PDIP-18 P	2.54 mm pitch; 7.62 mm rows	Narrow through-hole package
SOIC-18 SO	1.27 mm pitch; 7.50 mm body width	Wide SOIC, not a narrow 3.9 mm body
Other packages	20-lead TSSOP / QFN	Different contact maps; not interchangeable with18-pin views
Supply absolute maximum	7.0 V	Normal operation ends at5.5 V
I/O absolute range	−0.6 to VDD + 1.0 V	Stress limits, not recommended input levels
Storage temperature	−65 to +150°C	Unpowered

Review the exact orderable and fabrication allowances before using the downloadable original footprints.