BETATLC555Low-power CMOS timer
The familiar eight-pin timer, with a low-current CMOS core.
TLC555 is a CMOS timer with the same eight-pin arrangement as the bipolar NE555. Two comparators monitor an external timing capacitor, a latch remembers the current state, and an internal discharge switch resets the capacitor for the next interval. Its high input impedance permits small timing capacitors and low-power timing networks. This page selects commercial-grade TLC555CP in PDIP-8 and TLC555CDR in SOIC-8: recommended operation is 2–15 V and 0–70°C. Industrial TLC555I has a different 3 V minimum supply. Do not transfer the C-grade low-voltage limit to every suffix. The 5 V example uses RA = 10 kΩ, RB = 68 kΩ and C = 10 µF for approximately one blink per second. A 4.7 kΩ LED resistor keeps output loading light. The interactive calculation shows ideal steady-state timing; capacitor tolerance, leakage, startup and output loading affect real measurements.
