BETATypical startup16 V · UC3842A
Current-mode PWM controller
UC3842A Specifications
Review UC3842A electrical specifications, operating conditions and package details.
Package view
Key specifications
COMP sets the sense threshold below an internal clamp. The output latch prevents a second full pulse until the next clock cycle.
Maximum sense threshold1 V typical
Oscillator capability500 kHz maximum
Selected ambient0–70 °C
Package details
UC3842AN · PDIP-8
| Property | Details |
|---|---|
| Manufacturer | Texas Instruments |
| Part number | UC3842AN |
| Package | PDIP-8 |
| Connections | 8 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | PDIP-8 |
| Thermal reference | See operating and package limits |
Startup and bias
UC3842A variant only
Manufacturer specifications 6 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Startup threshold | 14.5–17.5 V; 16 V typical | VCC rising |
| Turn-off threshold | 8.5–11.5 V; 10 V typical | VCC falling after turn-on |
| Example supply | 18 V regulated | Allows margin above the maximum startup threshold |
| Startup current | 0.3 mA typical; 0.5 mA maximum | Specified test conditions |
| Operating supply current | 11 mA typical; 17 mA maximum | FB and ISENSE grounded; unloaded test conditions |
| Ambient temperature | 0 to +70°C | Selected UC3842A grade |
No specifications match. Try a parameter name or a unit.
The shared family operating table does not override the UC3842A startup threshold.
Reference and feedback
UC384xA specifications
Manufacturer specifications 7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Initial VREF | 4.9–5.1 V; 5 V typical | TJ = 25°C, IO = 1 mA |
| Total VREF variation | 4.82–5.18 V | Specified line, load and temperature |
| Normal VREF load | 10 mA maximum | Reference supplies timing and control networks |
| VREF bypass | 1 µF | Close to VREF8 and GND5 |
| FB regulation reference | 2.42–2.58 V; 2.5 V typical | VCOMP = 2.5 V |
| Amplifier unity bandwidth | 1 MHz typical; 0.7 MHz minimum | Manufacturer test conditions |
| Amplifier output | COMP1 | Compensation and current-demand control |
No specifications match. Try a parameter name or a unit.
VREF is not a motor or general power-supply output.
Timing and pulse limits
Eight-pin RT/CT4
Manufacturer specifications 7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| RT connection | VREF8 to RT/CT4 | Recommended resistor range 5–100 kΩ |
| CT connection | RT/CT4 to GND5 | Recommended capacitance 470 pF–4.7 nF |
| Example network | 10 kΩ and 3.3 nF | Matches the electrical-characteristic timing setup |
| Initial frequency | 47–57 kHz; 52 kHz typical | TJ = 25°C and stated datasheet conditions |
| Typical period | About 19.2 µs | 1 / 52 kHz |
| Maximum duty capability | 92% minimum; 96% typical | UC3842A test conditions |
| Other family members | UC3844A / UC3845A limit duty to about half | Do not mix their timing behavior with this page |
No specifications match. Try a parameter name or a unit.
Frequency and maximum duty are affected by discharge current and the RC network.
Current comparator
Voltage determines external peak current
Manufacturer specifications 7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Maximum sense input | 0.9–1.1 V; 1 V typical | VCOMP = 5 V; specified test |
| Sense control gain | 2.85–3.15 V/V; 3 typical | Specified current-sense transfer |
| Comparator delay | 150 ns typical; 300 ns maximum | ISENSE transition from 0 to 2 V |
| Shunt relationship | IPK ≈ VTRIP / RSENSE | Ignores propagation overshoot and filtering |
| Illustrative 0.5 Ω shunt | 1 V / 0.5 Ω = 2 A | Calculation only; no shunt or power stage in the bench demo |
| DC sense above threshold | Pulses are cut short | Propagation delay can leave narrow pulses |
| Duty above 50% | Slope compensation may be needed | Current-mode subharmonic behavior must be checked |
No specifications match. Try a parameter name or a unit.
Actual power-stage peak current also depends on delay, noise filtering, tolerances and inductor current slope.
18 V scope circuit
Observe current-comparator action
Manufacturer specifications 8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| VCC7 / GND5 | 18 V / common return | 10 µF and 100 nF local supply bypass |
| VREF8 | 1 µF bypass | Feeds RT and the sense-control divider |
| RT / CT | 10 kΩ from REF to pin 4; 3.3 nF from pin 4 to GND | Keep timing traces short |
| FB2 / COMP1 | GND / no external connection | Maximum current demand in this demonstration |
| Sense control | 30 kΩ in series with a 10 kΩ pot across REF/GND | Pot wiper gives approximately 0–1.25 V |
| ISENSE3 filter | Wiper through 1 kΩ; 1 nF from pin 3 to GND | Reduces wiper noise; not a power-stage filter design |
| OUTPUT6 | High-impedance scope plus 10 kΩ to GND | No transformer or switching MOSFET |
| Control action | Raise sense voltage from zero | Observe pulse truncation near the comparator threshold |
No specifications match. Try a parameter name or a unit.
All grounds share one return. The output can reach near VCC; use a properly rated probe.
Output and layout
Totem-pole gate drive
Manufacturer specifications 6 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Peak output capability | Up to ±1 A | Peak gate drive; observe thermal and pulse limits |
| LOW at 20 mA sink | 0.1 V typical; 0.4 V maximum | Specified VCC = 15 V test |
| HIGH at 20 mA source | 13.5 V typical; 13 V minimum | Specified VCC = 15 V test |
| External MOSFET connection | Use a suitable gate resistor | Limits peak gate charging current |
| Supply bypass sizing | VCC capacitance at least 10× VREF bypass | Also account for power-switch gate capacitance |
| Ground arrangement | Short local timing and sense returns | Keep gate-current loops away from analog inputs |
No specifications match. Try a parameter name or a unit.
The eight-pin version shares power and signal ground internally; larger packages have additional pins.
Packages and absolute limits
UC3842AN · PDIP-8
Manufacturer specifications 7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| PDIP reference | UC3842AN · 8 pins | TI P; current appendix marks NRND |
| SMD reference | UC3842AD8TR · 8 pins | TI D8; active orderable in reviewed appendix |
| Different SMD ordering | UC3842AD · 14 pins | Different pin map; not represented by this eight-pin preview |
| VCC absolute maximum | 30 V from a low-impedance source | Stress limit; not a recommended operating target |
| Analog-input absolute range | −0.3 to +6.3 V | Recommended analog limits are tighter |
| Storage temperature | −65 to +150°C | Unpowered |
| Output capacitive energy | 5 µJ absolute maximum | Check driver dissipation and repetition |
No specifications match. Try a parameter name or a unit.
Use exact suffixes and manufacturer drawings when selecting a package.
Connections by function
Select a pin for its function, connection guidance and electrical notes.