Explore W25Q32JV pins, signal names, electrical functions and connection guidance for each package.
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Click a lead or use the arrow keys. Top view
Frames each serial command. HIGH deselects the chip and releases the data outputs.
Connect to controller chip-select with a pull-up to 3.3 V; keep HIGH during power-up.
Program and erase commands must end on a complete byte boundary.
MISO in standard SPI; the second bidirectional lane in Dual/Quad operation.
Connect to controller MISO in the example.
Output changes with the falling serial-clock edge.
Third bidirectional data signal for Quad SPI instructions in the selected JV Q ordering variant.
Not used by the standard-SPI example; a 10 kΩ pull-up keeps the board net defined.
Do not relabel this selected part as /WP: the referenced IQ option starts with QE=1, enabling quad data; QE=0 selects /WP and /HOLD functions.
Supply and signal reference.
Connect to the controller ground and bypass return.
MOSI in standard SPI; the first bidirectional lane in Dual/Quad operation.
Connect controller MOSI to this pin.
Commands and standard input data are sampled on rising CLK edges, MSB first.
Clocks the selected SPI transaction.
Use controller SCLK; the example uses mode 0 at 1 MHz.
Maximum permitted frequency depends on command and supply voltage.
Fourth bidirectional data signal for Quad SPI instructions.
Unused by the standard-SPI example; 10 kΩ pull-up to 3.3 V.
This eight-lead package has no separate hardware /RESET pin.
Single 2.7–3.6 V supply.
Use 3.3 V and a 100 nF bypass close to pins 8 and 4.
Not a 5 V device; use compatible controller levels.
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