BETAStorage32 Mbit · 4 MiB
32-Mbit Dual/Quad SPI NOR flash
W25Q32JV Specifications
Review W25Q32JV electrical specifications, operating conditions and package details.
Package view
Key specifications
A serial command engine feeds address decoders, a page-program buffer and the NOR cell array. Status bits report whether an internal program or erase cycle is still busy.
Supply range2.7–3.6 V
Program page256 bytes
Industrial ambient−40–85 °C
Package details
W25Q32JVDAIQ · PDIP-8
| Property | Details |
|---|---|
| Manufacturer | Winbond Electronics |
| Part number | W25Q32JVDAIQ |
| Package | PDIP-8 |
| Connections | 8 pins |
| Mounting | Through-hole |
| Lead pitch | 2.54 mm |
| Package code | PDIP-8 |
| Thermal reference | See operating and package limits |
Memory organization
Binary sizes, addresses and boundaries
Manufacturer specifications 8 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Capacity | 32 Mbit / 4,194,304 bytes | 4 MiB, not 32 megabytes |
| Address range | 0x000000–0x3FFFFF | 24-bit address field for normal array commands |
| Program page | 256 bytes | 16,384 pages |
| Sector erase | 4 KiB | 1,024 sectors |
| Block erase | 32 KiB or 64 KiB | 128 or 64 blocks respectively |
| Erased state | 0xFF per byte | All bits are ones |
| Programming direction | 1 → 0 | Erase required for 0 → 1 |
| Page boundary | Split writes before it | Excess program data wraps within the selected page |
No specifications match. Try a parameter name or a unit.
Plan data structures around erase units and power-loss recovery.
Common standard-SPI commands
MSB first; separate CS transaction for each command
Manufacturer specifications 11 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Read JEDEC identification | 9F | Returns EF 40 16 for the reviewed device |
| Read data | 03 + 24-bit address | No dummy byte; clock ceiling 50 MHz |
| Fast read | 0B + address + dummy byte | Observe supply-dependent fast-command limit |
| Write enable / disable | 06 / 04 | Sets / clears Write Enable Latch |
| Read status register 1 | 05 | BUSY bit0, WEL bit1 |
| Page program | 02 + address + data | 1…256 bytes, without crossing a page |
| Erase 4 KiB sector | 20 + address | Requires Write Enable |
| Erase 32 / 64 KiB block | 52 / D8 + address | Requires Write Enable |
| Chip erase | C7 or 60 | Erases the entire array |
| Power-down / release | B9 / AB | Observe entry and recovery timing |
| Software reset sequence | 66 then 99 | Two command frames; allow reset recovery |
No specifications match. Try a parameter name or a unit.
Identification and read commands do not modify user memory. Programming, erasing and protection writes do.
Supply, logic and startup
Revision C selected industrial variants
Manufacturer specifications 9 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply | 2.7–3.6 V | Example: regulated 3.3 V |
| Industrial ambient | −40 to +85°C | I temperature grade |
| Input HIGH / LOW | ≥0.7×VCC / ≤0.3×VCC | Not 5 V tolerant |
| Normal 03 read clock | Up to 50 MHz | At specified supply range |
| Other supported command clocks | Up to 133 MHz | VCC=3.0–3.6 V; not every framing mode has identical throughput |
| Fast-command clock at 2.7–3.0 V | Up to 104 MHz | Meet AC timing and loading requirements |
| VCC valid to CS LOW | 20 µs minimum | Keep CS HIGH during startup |
| Delay before write instruction | 5 ms minimum | After power becomes valid |
| Local bypass | 100 nF in the example | Short loop between VCC8 and GND4 |
No specifications match. Try a parameter name or a unit.
The 1 MHz identification example is intentionally well below the speed ceiling.
Program, erase and recovery times
Typical values and maximum completion limits
Manufacturer specifications 9 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Page program | 0.7 ms typical / 3 ms maximum | Poll BUSY rather than delaying only the typical time |
| 4 KiB sector erase | 45 ms typical / 400 ms maximum | Target erase unit only |
| 32 KiB block erase | 120 ms typical / 1.6 s maximum | Larger erase scope |
| 64 KiB block erase | 150 ms typical / 2 s maximum | Larger erase scope |
| Chip erase | 10 s typical / 50 s maximum | Entire memory |
| Write status register | 10 ms typical / 15 ms maximum | Protection/configuration operation |
| Power-down entry | 3 µs maximum | After CS rises for B9 |
| Release without ID read | 3 µs maximum | Wait before next instruction |
| Software-reset recovery | 30 µs minimum | Wait before next command |
No specifications match. Try a parameter name or a unit.
Retain supply throughout a modifying cycle; power interruption can leave the affected data incomplete.
Variant and package distinctions
Read the exact part suffix and revision
Manufacturer specifications 7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Q ordering option | QE=1 factory default | QE is writable; Standard and Dual commands still available |
| Pin3 / pin7 | IO2 / IO3 | Quad data lanes; not /WP and /HOLD on this reference |
| Separate hardware RESET | Absent on these eight-lead packages | Available on specified larger packages |
| SOIC option shown | SS, 208-mil body | 5.28 × 5.28 mm nominal body |
| PDIP option shown | DA, 300-mil row format | 2.54 mm pitch |
| Other offered package families | VSOP, WSON, XSON, SOIC16, TFBGA | Not interchangeable footprints; not all displayed here |
| Orderability | Check current manufacturer/distributor listing | This page identifies the source revision and selected package definitions |
No specifications match. Try a parameter name or a unit.
Do not blindly substitute another W25Q32 family or suffix.
Read the device identity
3.3 V host, mode 0, 1 MHz
Manufacturer specifications 7 parameters
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| Parameter | Value | Conditions / notes |
|---|---|---|
| Supply and ground | VCC8 / GND4 | 3.3 V / common ground |
| SPI signals | CS1, DO2, DI5, CLK6 | Host CS, MISO, MOSI, SCLK |
| Defined idle nets | 10 kΩ pull-ups on CS, IO2 and IO3 | IO2/IO3 unused by this standard-SPI example |
| Transmit bytes | 9F 00 00 00 | CS LOW for the complete transfer |
| Receive bytes | XX EF 40 16 | Discard response during opcode |
| After transfer | CS HIGH | Data output releases |
| Interpretation | EF: Winbond; 40: type; 16: capacity code | Expected identification, not a measured live result |
No specifications match. Try a parameter name or a unit.
All logic is 3.3 V. Add level translation if the controller uses incompatible voltages.
Connections by function
Select a pin for its function, connection guidance and electrical notes.