Modified Sine Wave Design With Code

Hello friends, I hope you are doing well. In this tutorial, we will design the timing logic for a modified sine-wave inverter and study the original CD4047B and CD4017B approach. We will also develop an equivalent microcontroller timing example so you can see exactly how the positive, zero and negative intervals are produced.

This article follows our tutorials on the basics of inverter topologies, the major inverter components and the pure sine-wave inverter. A modified waveform is simpler than filtered SPWM, but its harmonic content limits the loads that should use it.

What Is a Modified Sine Wave?

A modified sine wave is a stepped bipolar waveform. During each cycle, the inverter applies a positive voltage, remains at zero, applies a negative voltage and returns to zero. It is also called a modified square wave or quasi-square wave.

The stepped output is not a sine wave with small imperfections. It is a different waveform with a strong harmonic spectrum. The zero intervals let us adjust RMS voltage and can reduce selected harmonics compared with a continuous square wave, but they do not provide the broad compatibility of a low-distortion sine source.

Modified Waveform Mathematics

Let the output magnitude be Vpk during the positive and negative plateaus. Let the two plateaus occupy a combined fraction D of the full period. The output is zero during the remaining fraction. Its RMS voltage is:

Vrms = Vpk × √D

If a transformer secondary produces plateaus of 325 V and we want 230 V RMS:

D = (Vrms / Vpk)² = (230 / 325)² = 0.501

The positive and negative plateaus together occupy about half the cycle. Each plateau therefore occupies approximately one quarter of the full cycle, with zero-voltage intervals occupying the other half.

This calculation matches RMS voltage only. It does not make the waveform equivalent to a 230 V sine wave. The sine wave has a continuously changing instantaneous voltage and a crest factor of approximately 1.414. Loads with transformers, induction motors, timing circuits, audio paths or phase-controlled inputs may behave differently on the stepped waveform.

Timing for a 50 Hz Output

A 50 Hz cycle lasts:

T = 1 / f = 1 / 50 Hz = 20 ms

For the 50% total conduction example, one cycle can contain four 5 ms intervals:

Time interval	Commanded output	Bridge state
0 to 5 ms	Positive plateau	Positive diagonal active
5 to 10 ms	Zero	Safe zero state or all switches off
10 to 15 ms	Negative plateau	Negative diagonal active
15 to 20 ms	Zero	Safe zero state or all switches off

A zero output command and dead time are separate concepts. The millisecond zero plateau shapes the modified waveform. Dead time is a much shorter blanking interval around switching transitions that prevents both devices in one bridge leg from conducting together.

Original CD4047B and CD4017B Circuit

The original circuit uses a CD4047B astable multivibrator as a clock source and a CD4017B Johnson counter to create a repeating sequence. Texas Instruments describes the CD4047B as a monostable or astable multivibrator with true and complemented buffered outputs. The oscillator output runs at twice the period rate of Q and complemented Q in astable mode.

The CD4017B is a five-stage Johnson counter with ten decoded outputs. Each positive clock edge advances one active decoded output, and each output remains high for one clock interval. By combining selected output intervals and resetting at the desired count, logic can produce timed windows for the two power-switch groups.

Use the exact timing equation and pin connections in the selected manufacturer's datasheet. The frequency depends on component tolerance, supply voltage, temperature and device characteristics. A nominal resistor and capacitor calculation is therefore followed by measurement.

Important Corrections to the Legacy Explanation

• A correctly loaded CMOS output does not normally produce only 1 V. Its guaranteed high and low levels depend on supply voltage and output current.
• Unused CMOS inputs must be tied to a defined logic level. Unused push-pull outputs must not be connected directly to ground or another output.
• The CD4017B has ten decoded outputs plus carry-out, not twelve decoded outputs.
• A MOSFET gate threshold is the beginning of conduction at a small test current. It is not the gate voltage for low-resistance, full-current operation.
• Logic inversion does not by itself create guaranteed dead time. Propagation delays vary with device, voltage and temperature.

Modified Sine-Wave Block Diagram

The complete signal path contains:

1. An oscillator or timer that defines the base timing.
2. Sequence logic that creates positive, zero and negative windows.
3. Interlocking and dead-time logic.
4. Gate drivers that supply the required gate voltage and current.
5. A push-pull or full-bridge power stage.
6. A transformer where voltage conversion and isolation are required.
7. Voltage, current and temperature protection.

The logic ICs should never be expected to drive large MOSFET gates directly. Their output current is limited, and slow gate transitions increase switching loss. A proper driver charges and discharges the gate rapidly and keeps the switch off during undervoltage or a fault.

Push-Pull Power Stage

A center-tapped transformer can be driven by two low-side MOSFETs. Turning on the first MOSFET applies battery voltage to one half of the primary. After it turns off and the blanking interval expires, the second MOSFET excites the other half with opposite magnetic polarity.

The two switches must never conduct together. Transformer leakage inductance also produces drain-voltage overshoot, so the MOSFET rating needs measured transient margin and a designed snubber or clamp.

Balanced volt-seconds are essential:

V1 × t1 ≈ V2 × t2

A systematic timing or winding imbalance can walk the core flux toward saturation. Saturation causes magnetizing current to rise sharply and can destroy a MOSFET even when average load power seems modest.

Full-Bridge Alternative

A full bridge uses four switches and a non-center-tapped winding. One diagonal produces the positive plateau and the opposite diagonal produces the negative plateau. A zero interval may turn all devices off or use a controlled freewheeling state, depending on load and driver design.

The bridge state table is:

Output state	Commanded pair	Main risk
Positive	Upper-left and lower-right	Wrong complementary device overlap
Negative	Lower-left and upper-right	Wrong complementary device overlap
Zero	Defined freewheel state or all off	Inductive current needs a valid path

Gate Resistors and Pull-Down Resistors

A resistor from gate to source gives the MOSFET a defined off state when the driver is high-impedance. A value such as 10 kΩ or 22 kΩ is common, but the value must be checked against leakage, noise and startup timing.

A separate series gate resistor controls peak driver current and edge speed. Its purpose differs from the pull-down resistor. Too much series resistance increases switching time and heat; too little may cause ringing, EMI or excessive driver current. Measure the gate-source waveform at the device with a suitable probe.

Choose gate-drive voltage from the MOSFET's specified on-resistance conditions and maximum gate-source rating. A threshold specified around 2 V to 4 V does not mean the device is fully enhanced at that voltage.

Equivalent Microcontroller Timing Code

A timer-based controller makes the sequence easier to adjust and supervise. The following AVR-style example describes a 50 Hz, four-state waveform using a 5 ms timer interrupt. The output functions are placeholders that must command an interlocked gate driver, not raw MOSFET gates.

#include <avr/io.h>
#include <avr/interrupt.h>

volatile uint8_t waveformState = 0;

static void all_switches_off(void)
{
    PORTB &= ~((1 << PB0) | (1 << PB1));
}

static void positive_command(void)
{
    all_switches_off();
    PORTB |= (1 << PB0);
}

static void negative_command(void)
{
    all_switches_off();
    PORTB |= (1 << PB1);
}

ISR(TIMER1_COMPA_vect)
{
    all_switches_off();

    switch (waveformState) {
        case 0:
            positive_command();
            break;

        case 1:
            /* Zero interval */
            break;

        case 2:
            negative_command();
            break;

        default:
            /* Zero interval */
            break;
    }

    waveformState = (waveformState + 1) & 0x03;
}

At 8 MHz with Timer1 prescaled by 64, the timer clock is 125 kHz. A 5 ms interval requires:

Counts = 125,000 × 0.005 = 625

For CTC mode counting from zero, OCR1A is 624. This produces four intervals in 20 ms and therefore 50 Hz.

The example gives millisecond waveform gaps, but it does not guarantee microsecond dead time within a gate-driver leg. Use driver hardware that prevents cross-conduction and a fault input that disables all gates immediately.

Expected Output

The logic waveforms should be non-overlapping and repeat at 50 Hz. At the transformer secondary, the ideal output has positive, zero and negative plateaus. Load current may not follow the same shape because inductive and capacitive loads store energy.

Verify these measurements in order:

1. Oscillator frequency and counter sequence at logic level.
2. Gate-driver outputs with the power stage disabled.
3. Dead time at the actual MOSFET gates.
4. Drain voltage and primary current from a current-limited low-voltage source.
5. Transformer secondary waveform with a safe resistive load.
6. Temperature and regulation over the intended load range.

Load Compatibility

Load type	Possible behavior on modified sine wave
Resistive heater	Often responds mainly to RMS voltage, subject to rating and controls
Incandescent lamp	Usually operates, but inrush still affects surge sizing
Induction motor	May buzz, heat, lose torque or run inefficiently
Transformer input	May produce acoustic noise and additional heating
Audio equipment	May reproduce harmonic noise
Timing or phase-control circuit	May misread zero crossings or waveform timing
Switch-mode power supply	Compatibility depends on rectifier, PFC and manufacturer specification

Protection and Safety

Add a source-side fuse, reverse-polarity protection, hardware current limit, battery undervoltage cutoff, output fault shutdown and thermal protection. A transformer primary fault can draw hundreds of amperes from a battery, so firmware alone is not enough.

An inverter producing 120 V or 230 V can cause fatal shock and fire. The transformer, PCB spacing, connectors, fuse, earthing and enclosure must meet the required safety standard. Do not use a solderless breadboard for the power stage, and do not connect an experimental inverter to household wiring or the utility grid.

Troubleshooting

Problem	Likely cause	Check
MOSFETs fail immediately	Shoot-through, gate overvoltage or drain transient	Gate overlap, driver supply, snubber and current trip
Transformer current rises at no load	Flux imbalance or core saturation	Primary symmetry, frequency, volt-seconds and winding
Output RMS is low	Large zero interval, battery sag or winding loss	Timing duty, bus voltage and primary current
Logic sequence is erratic	Floating CMOS input or poor decoupling	Tie every unused input and add local bypass capacitors
Load makes audible noise	Expected harmonic excitation	Use a sine-wave inverter when the load requires one

Practical Review

A modified sine-wave inverter produces positive, zero and negative voltage plateaus. The zero duration sets RMS voltage but does not remove the waveform's substantial harmonics. A CD4047B and CD4017B can create a repeatable sequence, while a timer-based microcontroller makes timing and protection easier to coordinate.

The most important power-stage requirements remain the same in both cases: strong gate drive, guaranteed dead time, balanced transformer excitation, measured transient control and hardware fault shutdown. Logic signals should be proven before the high-energy stage is connected.

Frequently Asked Questions

Is a modified sine wave a low-resolution pure sine wave?

No. It is a stepped waveform with zero intervals and substantial harmonics. It can match the RMS value of a sine wave without matching its instantaneous voltage or spectrum.

Why use the CD4017B?

Its decoded outputs become active sequentially, so selected time slots can create the positive, zero and negative pattern. The reset input can shorten the sequence to the required number of states.

Should unused CD4017B outputs be grounded?

No. Unused push-pull outputs are left unconnected. Unused CMOS inputs must be tied to a valid high or low level according to the datasheet.

Does MOSFET threshold voltage tell me the correct gate-drive voltage?

No. Threshold is measured at a very small drain current. Use the gate voltage at which the datasheet specifies on-resistance, while staying below the maximum gate-source voltage.

Why is dead time required if the signals are inverted?

Real devices have unequal propagation, rise and fall delays. One MOSFET can remain on after its command changes while its complement begins turning on. Interlocking and dead time cover that transition.

Can an LC filter turn this waveform into a perfect sine wave?

A filter can attenuate harmonics, but a low-frequency stepped waveform requires large magnetics and interacts strongly with the load. High-frequency SPWM is the normal approach when low-distortion sine output is required.

Can every appliance run from a modified sine-wave inverter?

No. Use it only when the appliance manufacturer permits that waveform. Motors, transformers, audio systems and waveform-sensitive controls are common problem cases.

Is this circuit suitable for grid connection?

No. Grid-tied inverters require synchronized current control, anti-islanding, certified protection and regulatory approval. This tutorial describes a stand-alone waveform generator.