Introduction to Multilevel Inverters

Hello friends! Today we will study multilevel inverters, starting with the switching waveform and then looking at the circuits that produce it. An inverter converts electrical power from a DC source into an AC output. Its switches determine the instantaneous voltage, while the modulation, load and filter determine how closely the useful output follows the required sine wave.

In our earlier tutorials on pure sine wave inverter design and modified sine wave inverters, the main question was how to generate the alternating waveform. Here we will introduce intermediate voltage steps and examine what they change. More steps can improve waveform quality, but they also introduce more devices, measurements and control decisions.

We will compare cascaded H-bridge, diode-clamped and flying-capacitor topologies. Along the way, we will calculate level counts, distinguish phase voltage from line voltage, and outline a simulation procedure. Keep a pencil beside you: writing down the voltage reference and tracing a switching state often explains more than memorizing a topology name.

What Is a Multilevel Inverter?

A multilevel inverter generates an output with several discrete voltage values by selecting among DC potentials or combining the outputs of converter cells. Those values form a staircase or a pulse-width-modulated waveform. The desired AC fundamental is one component of that waveform; the remaining frequency components are harmonics and switching ripple.

Some familiar inverter descriptions classify different things. Square wave and sinusoidal PWM describe waveform generation. Grid-connected and standalone describe operating roles. Cascaded H-bridge describes circuit construction. A grid-connected solar converter can therefore also be a multilevel sinusoidal-PWM inverter. Treating these descriptions as mutually exclusive categories creates unnecessary confusion.

Specify where the voltage is measured

Consider a conventional two-level half bridge supplied from a total DC link V_dc. Relative to the negative DC rail, its ideal pole voltage takes values 0 and V_dc. Relative to the midpoint of a balanced split supply, those same states become −V_dc/2 and +V_dc/2. The circuit has not changed; only our reference has changed.

A full bridge contains two such legs. Its differential output can have −V_dc, 0 and +V_dc, depending on the switching method. Consequently, seeing three values across a load does not by itself prove that each inverter leg is a three-level topology. Always identify whether a diagram shows a pole, phase-to-neutral or line-to-line voltage.

The two-level PWM illustration shows why an average voltage can track a reference even though the instantaneous voltage remains switched. Changing pulse widths changes the average over a switching interval. An inductive load or designed filter reduces high-frequency current ripple; it does not turn the unfiltered pole voltage itself into a continuous sine wave.

Why Add More Voltage Levels?

Intermediate levels can reduce the voltage change associated with an individual commutation. For an ideal three-level neutral-point-clamped leg with a balanced link, adjacent pole states differ by V_dc/2 rather than the full link voltage. This can help manage ripple, insulation stress and electromagnetic interference when the switching sequence actually uses adjacent levels.

However, voltage-step magnitude and edge speed are different quantities. Approximately, dv/dt = ΔV/Δt. A 200 V transition completed in 100 ns has an average slope of 2 V/ns. If a different device completes a 100 V transition in 20 ns, its slope becomes 5 V/ns. A smaller step alone does not guarantee a slower electrical edge.

The three-, five- and seven-level illustration makes the staircase easier to visualize. Additional levels offer more freedom to approximate a sinusoid. Actual distortion still depends on switching angles, modulation, source balance, dead time and the load. More levels should therefore be evaluated under a defined operating condition rather than advertised as an automatic improvement in every measurement.

A useful distortion calculation

Voltage total harmonic distortion is THD_v = √(V₂² + V₃² + …)/V₁, where the V terms are RMS harmonic amplitudes. For an illustrative 100 V RMS fundamental with only 6 V and 8 V RMS harmonics included, THD is √(36 + 64)/100 = 10%. Report the harmonic bandwidth and measurement point when quoting this result.

Current THD may be much lower than voltage THD for an inductive load, because impedance increases with frequency. Neither number can substitute for the other. A fair comparison also uses the same fundamental output, load, sampling method and treatment of the startup transient.

Cascaded H-Bridge Multilevel Inverters

A cascaded H-bridge, or CHB, connects the AC outputs of several full-bridge cells in series. Each cell has its own DC supply arrangement and can produce a positive, zero or negative output. The phase voltage is the algebraic sum of the cell voltages. The series connection is on the AC side; connecting all DC supplies together can defeat the isolation required by the arrangement.

For s cells with equal DC voltages V_cell, the ideal phase output has 2s + 1 distinct levels. The switch count is 4s controlled devices per phase, excluding gate drivers, protection and auxiliary circuits. Two cells give five levels and eight switches; four cells give nine levels and sixteen switches. These counts apply to this particular symmetrical CHB construction.

Several combinations can create the same total voltage. For example, either cell can supply the positive 100 V step while the other supplies zero. The controller may choose among these redundant states to distribute switching or energy demand. That choice matters when the cells are powered by batteries or photovoltaic sources with unequal conditions.

Understand the switching paths

Within one H-bridge, a diagonal switch pair applies positive or negative voltage across the output. Appropriate same-rail states provide zero differential voltage. The upper and lower switches of one leg must not conduct together, because that shorts the cell supply. Turning every switch on is therefore a fault, not a valid way to turn the inverter off.

With an inductive load, current cannot stop instantaneously when a gate command changes. Freewheeling paths, device diodes and dead time become part of the real switching behavior. A voltage-state table is the starting point; a complete design must also trace current for both polarities through every allowed transition.

The three-phase illustration extends the cell arrangement to three phase strings. Phase references are normally separated by 120 electrical degrees. For a wye system, line voltage is the difference between phase voltages, such as v_ab = v_a − v_b. Its level count and waveform can differ from those of one phase string.

The transformer-coupled illustration shows another way of combining converter contributions while providing isolation or voltage transformation. Transformer ratios, flux balance and leakage inductance become additional design variables. A transformer does not remove the need to control each cell or guarantee that arbitrary DC sources can safely share a connection.

Strengths and limitations of CHB

CHB is attractive when modular cells and suitable isolated supplies are available. A failed or serviced cell can sometimes be handled through a deliberately designed bypass strategy, although fault tolerance is not automatic. Separate gate supplies, communications and protection can offset the apparent simplicity of the repeated bridges.

Asymmetric CHB arrangements deliberately use unequal DC voltages to create additional output combinations. The formula 2s + 1 no longer describes every case. You must enumerate the sums, check device voltage ratings and decide how the source energies remain balanced. Unequal sources are a design choice, not a shortcut that preserves all symmetrical operating assumptions.

Diode-Clamped or Neutral-Point-Clamped Inverters

A diode-clamped inverter divides a DC link into capacitor sections and uses clamping paths to access intermediate potentials. The familiar three-level neutral-point-clamped, or NPC, leg has four controlled switches and two clamping diodes. With a balanced split link, its pole output relative to the midpoint is +V_dc/2, zero or −V_dc/2.

For a conventional m-level diode-clamped leg, the usual idealized count is 2(m − 1) controlled switches, m − 1 DC-link capacitor sections and (m − 1)(m − 2) clamping diodes when counted as unit-voltage-rated devices. Capacitor sections can be shared across phases. Physical diode arrangements and ratings can change the packaged device count.

Here V_dc means the entire link voltage. Under ideal balance, each capacitor section carries V_dc/(m − 1). Avoid using the same symbol for both the full link and one section; that notation error can produce seriously wrong switch-voltage calculations.

The retained six-level, three-phase diagram illustrates the growth in connections at higher level counts. In the conventional balanced interpretation, five link sections establish six accessible potentials. If the total link is 500 V, each section is nominally 100 V. Device blocking stress must still be checked during transitions, imbalance and faults rather than inferred solely from this division.

Use the associated waveform illustration to distinguish phase and line voltages. Intermediate levels depend on actual capacitor voltages. If one section drifts from its target, a nominally uniform staircase becomes uneven, which changes the fundamental and harmonic spectrum even when the gate timing remains unchanged.

Why neutral-point balance matters

Different switching states draw different currents from the split link. The control system needs to keep the capacitor voltages near their references across the intended operating range. Startup precharge establishes a controlled initial condition; it does not guarantee permanent balance. Measure individual capacitor voltages in simulation instead of looking only at their sum.

NPC converters are useful in applications such as motor drives and grid conversion where the topology fits the DC supply and voltage rating. A conventional inverter stage alone does not provide every function of a complete HVDC transmission system. Rectification, isolation where required, protection and system-level control remain separate engineering responsibilities.

Flying-Capacitor Multilevel Inverters

Flying-capacitor converters use charged capacitors within the switching structure to establish intermediate voltages. Certain redundant switching states charge a capacitor, while others discharge it, depending on current direction. The controller must select those states to maintain the intended voltages while producing the requested output.

The retained five-level illustration introduces the ladder of capacitor potentials. Do not confuse the DC-link divider with the additional flying capacitors. In the conventional m-level structure, 2(m − 1) controlled switches are used per leg; a commonly quoted count of flying capacitor units is (m − 1)(m − 2)/2 when expressed in equal voltage-rated units. Implementations using capacitors with different ratings can have different physical counts.

The essential lesson is the stored voltage, not the count alone. Each capacitor needs an appropriate voltage rating, ripple-current capability and initial charging procedure. A simulation that simply assigns perfect starting voltages can hide the practical difficulty of achieving them and maintaining balance during changing load current.

Flying-capacitor circuits can provide useful redundant states and favorable ripple behavior. They are not inherently inefficient merely because they use capacitors. Losses depend on device selection, switching frequency, conduction paths and capacitor ESR. Texas Instruments compares these practical tradeoffs with NPC, ANPC and T-type arrangements in its converter topology discussion.

The controlled switches may be IGBTs or MOSFETs, selected for the required voltage, current and switching frequency. Their gate requirements and reverse-current behavior differ. A generic ideal switch model cannot establish switching energy, junction temperature or diode recovery loss. Use appropriate device models and measured or specified parameters when moving from topology exploration to a loss calculation.

Compare the Three Topologies

No row is universally cheapest or best. Count isolated drivers, sensors, cooling, precharge and protection alongside the main switches. An attractive ideal waveform is only one part of a converter that must start reliably, survive disturbances and operate over a specified load range.

Modulation and a Practical Simulation Workflow

Multilevel sinusoidal PWM compares a sinusoidal reference with appropriately arranged carriers. Selective harmonic elimination chooses switching angles to meet a fundamental-voltage target and suppress selected harmonics. Space-vector approaches choose available voltage vectors and their dwell times. These are different control tools; topology does not uniquely determine modulation.

For background on these families, see Rodríguez, Lai and Peng's survey of multilevel inverter topologies and control. For a concrete modern implementation, TI's three-level T-type reference design demonstrates the additional sensing and control surrounding a power stage. A T-type leg is related to the discussion but should not be relabeled as the conventional diode-clamped circuit above.

1. Define the DC link, desired fundamental voltage and frequency, load and measurement reference.
2. Build one ideal cell or leg and verify every allowed output state before adding PWM.
3. Add the other cells or phases and check signs, source isolation and initial capacitor voltages.
4. Implement interlocks and dead time appropriate to the switching arrangement.
5. Record output voltage, load current, each capacitor voltage and relevant switch stresses.
6. After startup has settled, measure RMS fundamental and harmonics over a stated window.
7. Repeat with load changes, unequal source voltages and a smaller simulation step to identify fragile assumptions.

The original article linked a three-level diode-clamped MATLAB/Simulink project. That historical project link remains for continuity; check the listing for current availability and supported software. The calculations here explain the method and are not a claim that the archived model has been rerun in a current release.

Review and Troubleshooting

If your output has the wrong number of steps, first inspect the measurement reference and individual cell states. If the steps are uneven, inspect DC sources and capacitor balance. If current grows unexpectedly, inspect shoot-through, load parameters and the startup condition before changing the controller gains.

If the spectrum looks unusually good, check whether an ideal filter or an unsuitable FFT window is hiding ripple. If it looks unusually poor, verify that the window contains complete fundamental cycles after settling. These checks help separate a genuine topology limitation from a measurement or implementation mistake.

Frequently Asked Questions

Does a multilevel inverter produce a pure sine wave?

Its switching output contains discrete levels and harmonics. Modulation and filtering can make the useful voltage or current approximately sinusoidal, but waveform quality must be measured at a specified point.

How many cells produce a five-level CHB output?

Two equal-voltage full-bridge cells connected in series produce five phase-output levels. That result assumes symmetrical supplies and the normal positive, zero and negative states of each cell.

Are more levels always more efficient?

No. More levels can reduce switching stress or filtering demand, while additional devices introduce conduction, drive and auxiliary losses. Compare efficiency at the same operating point and include the supporting circuits.

Can I ignore capacitor balance in an introductory model?

You can begin with ideal balanced voltages to learn switching states, but label that assumption. A useful next model allows capacitor voltages to change and shows whether the controller maintains balance under load.

What should I understand before building hardware?

Be able to trace current paths, explain forbidden switching combinations and calculate expected voltage stress. Begin with an isolated low-voltage learning setup; simulation waveforms alone do not establish the electrical protection of a physical converter.