I am an M.tech student and have been working on a project related to FPGA architecture research.In this, among other things i am supposed to convert verilog files into BLIF format as a part of technology mapping.While some files are getting neatly converted,some files do not.I dont understand why. B'cuz the files which are not getting converted too are functionally correct and do get compiled in MODELSIM. Please get back to me on this as its really urgent. Small Bio