Traffic Signal Control using 555 Timer in Proteus ISIS

Hello friends! Today, we will build a traffic-signal demonstration using a 555 timer and a CD4017 counter in Proteus ISIS. The timer supplies a repeating clock, the counter advances through ten states, and a few diodes combine those states into red, yellow and green indications. This is a useful introduction to sequencing without a microcontroller.

We will keep the original project's teaching flow, but make the timing and output connections more precise. In particular, the CD4017 is a decade counter with decoded outputs, not a serial-data shift register. Its clock input advances a sequence; it does not receive a stream of data bits describing the lamp colors.

Our goal is a small educational display. We will calculate the state duration, explain the overlap between red and yellow, and identify the electrical limits that an ideal simulation can hide. A demonstration with three LEDs is not a controller for a public road or an installation with conflicting traffic movements.

Divide the Circuit into Three Functions

It is easier to understand the design when each part has a clear job. The clock generator determines how frequently the state changes. The counter remembers which state is active. The output network determines which LEDs are illuminated in that state.

Changing the timer's period changes every state's duration together. Changing the diode connections changes the color pattern. These are separate adjustments, so we should not modify both at once while troubleshooting.

The original component collection is shown below. Place the timer and counter with enough space between them to label the clock, supply, reset and lamp connections. Clear signal names are more helpful than a compact drawing full of crossing wires.

Understand the CD4017 Counter

The CD4017B contains a Johnson counter and decoding logic that provides ten sequential outputs. During normal operation, one of Q0 through Q9 is high. A rising clock edge advances the active output when clock inhibit is low. After Q9, the sequence returns to Q0.

A high reset input forces the sequence to Q0. Reset therefore does not mean every output is low. If a red indicator is selected in Q0, resetting produces red. The carry output is a different signal: it is high for the first five count states and low for the following five.

These functions and pin assignments are defined in the Texas Instruments CD4017B datasheet. Check the device name and package when moving from a Proteus symbol to a physical IC.

Read the Actual Color Sequence

The original circuit uses the carry output for red, Q4 and Q9 for yellow, and Q5 through Q8 for green. Because carry remains high at Q4, the fourth advance produces red and yellow together. The circuit therefore has four distinct visible phases, even though there are only three LED colors.

This is an illustrative sequence with red-only, red-plus-yellow, green-only and yellow-only intervals. Do not describe the yellow indication as having one universal meaning for every country or signal system. For the electronics lesson, the important point is that the wiring and the state table agree.

The historical schematic is retained below. Its supply and LED resistor choices should not be copied without checking the output-current limits; we will use a lower-current version for the revised design.

Build the Timer Clock

For a consistent 5 V demonstration, use a TLC555 CMOS timer with a CD4017B powered from the same regulated supply. A CMOS timer is useful here because its lightly loaded output can approach the supply rails. A bipolar NE555 has different output characteristics, so logic-level compatibility must be checked rather than assumed.

Connect timer pin 1 to ground, pin 8 to 5 V and reset pin 4 to 5 V. Join trigger pin 2 and threshold pin 6 at the capacitor node. Connect R_A from the supply to discharge pin 7 and R_B from pin 7 to the capacitor node. Connect the timing capacitor from that node to ground.

Connect a 10 nanofarad capacitor from control pin 5 to ground and a 100 nanofarad supply bypass capacitor close to the timer. Also bypass the counter locally. The timing capacitor is not a substitute for these supply connections.

During charging, the capacitor rises from approximately one-third to two-thirds of the supply through R_A and R_B. During discharge, it falls through R_B. The thresholds depend on the supply; they are not a fixed 5 V trigger level. At a 5 V supply, the nominal thresholds are about 1.67 V and 3.33 V.

Calculate High Time, Low Time and Period

For the standard astable connection, t_H ≈ 0.693(R_A + R_B)C and t_L ≈ 0.693R_BC. The total period is T ≈ 0.693(R_A + 2R_B)C, and frequency is f = 1/T.

Choose R_A = 10 kilohms, R_B = 68 kilohms and C = 10 microfarads. The calculated high time is about 0.541 seconds and low time about 0.471 seconds, giving T ≈ 1.012 seconds and f ≈ 0.988 Hz.

The counter advances once per rising edge, so one count lasts a complete clock period, not just the output-high interval. Four consecutive states therefore last approximately 4.05 seconds. This distinction is easy to miss when watching only the timer's LED or voltage level.

The original drawing uses a larger 47 microfarad timing capacitor with two 22 kilohm timing resistors. For a standard astable connection, those values give a nominal period of about 2.15 seconds. The capacitor does not create an arbitrary lag; it participates in a repeated charge-and-discharge cycle with calculable thresholds.

Calculate the Phase Durations

These are steady-cycle durations. Immediately after a manual reset is released, the time until the next rising edge depends on the clock's current phase. The first red interval may therefore differ from later full cycles unless clock and counter initialization are coordinated.

Component tolerances affect every phase. A ±20% timing capacitor already introduces substantial uncertainty before resistor tolerances and leakage are considered. This circuit is suitable for observing sequence logic, not for claiming precise elapsed-time performance.

If you need different timing ratios, change how many counter states feed each phase. Changing the capacitor alone multiplies all phase durations by approximately the same factor. Arbitrary independent durations usually require a more flexible state machine or counter arrangement.

Use Diodes to Combine Counter Outputs

Connect a diode anode to each counter output that should activate a shared lamp. Join the cathodes for that lamp at a common node. From that node, connect the lamp's series resistor and LED to ground. This arrangement allows any selected high output to supply the lamp without directly connecting it to other outputs that are low.

For green, use four separate diodes from Q5, Q6, Q7 and Q8. For yellow, use two separate diodes from Q4 and Q9. Red can be connected through its own resistor to the carry output. Do not join push-pull counter outputs directly, even though only one decoded output is high at a time.

The diode forward drop reduces the voltage available to the LED and resistor. Its exact value depends on current and temperature. At the low currents used here, assuming a fixed 0.7 V is only a rough design estimate, so check the simulated or measured node voltages when evaluating brightness.

Respect the Counter's Output Current

The 100 ohm LED resistors in the original 12 V drawing suggest currents far above what a CD4017B should be expected to source while maintaining a valid high output. Ignoring the output limitation, even (12 − 2)/100 would imply 100 mA for a red LED. That is not a sensible direct counter-output load.

For the revised 5 V demonstration, start with 10 kilohm resistors and efficient indicator LEDs. Assuming a 4.6 V output, 0.6 V diode drop and 2.0 V LED drop gives approximately (4.6 − 0.6 − 2.0)/10,000 = 0.20 mA. The direct red branch would draw about 0.26 mA with the same assumptions.

These low currents suit an indicator experiment much better than trying to power bright lamps directly. Confirm the worst-case source capability of your chosen counter and operating conditions. If greater brightness is required, add designed output buffers with appropriate input loading and lamp-current ratings.

Do not increase the supply just to make the LEDs brighter. A supply change affects logic compatibility, timer limits, LED currents and capacitor ratings together. Review the whole circuit whenever changing the voltage.

Reset and Pause the Sequence Deliberately

Connect clock inhibit to ground for normal counting. Connect reset to ground through a 10 kilohm resistor and provide a momentary button from reset to 5 V. Pressing it selects Q0 and therefore red. Release it to permit counting.

This manual reset arrangement is simple to understand, but it does not guarantee the power-up state without a reset action. If deterministic startup is required, add a reset circuit whose pulse width and supply-ramp behavior are specified. A capacitor placed somewhere on reset is not automatically a reliable power-on-reset design.

To pause, clock inhibit can be driven high using a properly defined control signal. Return it low away from an active clock transition; mechanical switch bounce and asynchronous control changes can otherwise produce confusing results. In a teaching simulation, use clean logic controls first and investigate switch behavior afterward.

Run the Proteus Demonstration Step by Step

1. Check that both ICs share the intended supply and ground.
2. Verify the timer capacitor polarity and all reset connections.
3. Start the simulation and pulse the counter reset.
4. Observe Q0 and the red LED before counting begins.
5. Monitor clock pin 14 with a probe and follow successive rising edges.
6. Check the four visible phases against the state table.
7. Measure a complete ten-state cycle after startup has settled.
8. Change only one timing component and compare the new period.

The original illustrated operating states are shown below. They help visualize the colors, but the complete state table explains the red-yellow overlap and the yellow-only interval more accurately than three isolated pictures.

For debugging, slow the clock or temporarily use a clean manual pulse source. Observe Q0 through Q9 directly before connecting the diode network. If the counter sequence is correct but a lamp behaves incorrectly, concentrate on its diode orientation, resistor and LED polarity.

When measuring the clock, place one cursor on a rising edge and the second on the next rising edge. Measuring from a rising edge to a falling edge gives only the high time. For the sequence period, compare two successive entries into Q0 after normal counting has begun. This separates clock duty cycle, count duration and complete-cycle duration, three quantities that are often incorrectly called the delay.

As an exercise, sketch a new allocation before moving any wires. If red-only occupies five states, yellow-only one and green-only four, the total is still ten states, but the carry-output shortcut no longer implements the desired red interval independently of the other mapping. Derive the required outputs from the new table rather than retaining connections simply because they worked in the previous version.

Troubleshooting and Design Review

The revised example gives us a transparent sequence with limited direct LED loading. It still has no independent watchdog, conflict monitor, lamp-failure feedback or defined fault-response architecture. A stopped clock could leave green illuminated indefinitely. That is acceptable as a fault to study on a classroom display, but it demonstrates why this circuit is not a road controller.

For a two-direction model, do not simply connect a second green LED wherever the first is off. Define every combined state, including clearance intervals, and ensure conflicting greens are impossible in the intended sequence. Then examine reset, loss of clock and power interruption separately from normal operation.

Our related projects on sequential LED blinking and capacitive touch sensing in Proteus explore other combinations of timers, input signals and output logic. The same habit applies in each: identify what every component actually controls before interpreting the display.

Frequently Asked Questions

Is the CD4017 a serial-in, parallel-out shift register?

No. It is a decade counter with decoded outputs. Each permitted clock edge advances its state; the circuit has no serial data input for loading arbitrary lamp patterns.

Why do red and yellow turn on together?

At Q4, the carry output is still high and the Q4 diode also powers yellow. That overlap follows directly from the chosen wiring.

Does a larger capacitor lengthen only the green phase?

No. It slows the clock and lengthens every state. Change the state allocation if you need a different ratio between phase durations.

Can the outputs drive a relay or high-power lamp directly?

They should not be treated as power drivers. Use a properly designed interface and check its input loading, current rating and protection requirements.

Where is the original simulation download?

The retained article data does not contain an attached simulation archive. The wiring instructions and original images are provided here without inventing a download link.

Has the revised hardware been measured?

No fresh hardware or Proteus run is claimed. The revised values and state table provide a design to evaluate, while the screenshots document the historical circuit.