LED Blinking using 555 Timer

Hello friends! Today we will make six LEDs light in a back-and-forth sequence using a 555 timer and a CD4017 decade counter. This extends our multiple LED flasher: instead of switching two whole banks, we will select a different position after each clock pulse.

The timer controls how quickly the pattern advances. The counter decides which of ten states is active, and an output-mapping network converts those ten states into a six-position outward-and-return pattern. Separating those jobs makes the circuit easier to understand and troubleshoot.

The original screenshots and download remain below. We will correct the description of the 4017 and replace the old output-combining method with diode isolation. Resistors between opposing outputs do not turn those outputs into a proper logic OR function.

Understand the Three Circuit Blocks

The first block is a repeating clock. The second is the CD4017, which advances through ten decoded outputs. The last block consists of output-isolation diodes, current-limiting resistors and LEDs arranged in the desired physical order.

The CD4017 is a decade counter with decoded outputs, internally based on a Johnson counter. It is not a general-purpose serial-in, parallel-out register into which you shift ten arbitrary data bits. The distinction matters because there is no serial data input in this project.

The TI CD4017B datasheet describes its clock, reset, clock-inhibit and decoded outputs. After reset, Q0 is active. With counting enabled, each rising clock edge advances the active state to the next output, and the sequence wraps after Q9.

Identify the Counter Pins

A standard CD4017B package has 16 pins, not fifteen. Ten are decoded count outputs, but that does not make it a ten-bit data register. The remaining pins provide power and control functions.

Check package orientation before wiring. Physical pin numbers are not in Q0-to-Q9 order around the package. Using a pin table avoids the common mistake of connecting LEDs according to adjacent pin positions.

Place local supply bypassing at both ICs. Give every control input a defined level, and leave unused outputs unconnected. An unused output is not an input that needs to be tied to ground.

Build a Slow Clock First

Use a standard 555 astable with R_A = 10 kΩ, R_B = 68 kΩ and C = 1 µF. Connect pins 2 and 6 together, place R_A between supply and pin 7, R_B between pin 7 and the timing node, and C from the timing node to ground.

Connect reset pin 4 high, ground pin 1 to ground, supply pin 8 to the chosen rail, and use the recommended supply and control-pin bypass capacitors. Pin 3 supplies the clock. No LED load should be attached directly to that clock line during the initial test.

For a 5 V CMOS logic build, a TLC555 CMOS timer is a suitable family to consider for the clock because its lightly loaded output can approach the rails. If using the historical bipolar 555 model, check its actual high voltage against the CD4017's input-high requirement. Matching supply labels alone does not prove logic compatibility.

The nominal period is 0.693(R_A + 2R_B)C, approximately 0.1012 s. This gives about 9.88 advances per second. Use a larger capacitor for a slower pattern while learning to follow the states.

Each output state lasts one complete clock period, not only the timer's high interval. The counter advances on an edge and retains its state between edges. The timer's duty cycle and the LED position dwell time are therefore different quantities.

Map Ten Counter States to Six LEDs

Arrange the six LEDs physically as D6, D5, D4, D3, D2 and D1 from left to right. The historical labeling is preserved here so that the screenshots and new table can be compared directly.

After Q9, the next edge selects Q0 and D6 again. The counter always counts forward internally. The apparent reverse motion comes from mapping later counter states back toward the left side of the display.

There are ten states rather than twelve because the two endpoints are not repeated on reversal. The pattern is D6, D5, D4, D3, D2, D1, D2, D3, D4, D5, then D6 again.

Do Not Directly Combine Counter Outputs

The original diagram combines several outputs through low-value resistors. When one output is high and the paired output is low, current can flow from one output stage into the other. This wastes current, reduces the LED-driving voltage and can exceed appropriate output loading.

For example, an idealized 5 V difference across two 100 Ω resistors in series would imply 25 mA between the outputs before accounting for their internal resistance and the LED load. The actual CMOS output voltage will change under load, so this is a warning calculation rather than a prediction of an acceptable operating point.

Use isolation diodes to implement the required OR connection. For each participating counter output, connect a diode anode to the output and its cathode to that LED's shared drive node. Current can then flow from the selected high output toward the LED without feeding a paired low output.

For D5, use separate diodes from Q1 and Q9. Repeat this arrangement for D4 from Q2 and Q8, D3 from Q3 and Q7, and D2 from Q4 and Q6. D6 and D1 each have one output; including a diode in those paths also makes their voltage drop more comparable.

A small signal diode such as a suitably specified 1N4148 can serve this low-current demonstration. Connect one LED resistor from each shared diode-cathode node to its LED anode, with the LED cathode at ground. Keep the diode orientation consistent across all ten paths.

Choose a Modest LED Current

The CD4017 is a logic device with limited output-drive capability. Begin with efficient indicator LEDs and a low current. A 6.8 kΩ resistor at 5 V, assuming a 0.6 V diode drop and 2 V LED drop, gives an idealized current of about 0.35 mA.

The loaded output voltage and actual diode and LED characteristics determine the real value. Check the datasheet at the intended supply and temperature. A large maximum-output-current number is not a guarantee that the output remains a valid near-rail voltage under that load.

If the indicators are too dim, add appropriate LED drivers instead of simply reducing the resistors until the logic outputs are heavily loaded. A transistor driver stage needs its own base or gate interface and current-limiting design.

Each LED still needs a resistor even though only one position is normally active. The counter determines which position is selected; it does not provide a regulated LED current. A single shared resistor can also give unwanted behavior during transitions or alternative patterns.

Follow the Original Forward Sequence

After reset, Q0 selects D6. This is the starting position in the original left-to-right arrangement. Check the logic state at Q0 rather than relying only on the LED's graphical brightness.

The first clock edge after reset release selects Q1 and therefore D5. Q0 should return low. If both LEDs remain strongly on, inspect the output mapping, diode orientation and whether the counter actually changed state.

The next edge selects Q2 and D4. At this point, the visual pattern has advanced two positions, while the counter has simply moved to its third decoded state.

Q3 selects D3. The physical center is not a special control state; it is just another mapping entry. This is why rearranging the LEDs can change the appearance without changing the counter logic.

Q4 selects D2. Its second diode input, Q6, remains low and isolated during this forward pass.

Q5 selects D1 at the far end. The next state, Q6, returns to D2 through that LED's second diode path. The subsequent states return through D3, D4 and D5 before wrapping to D6.

The original sequence table illustrates the same visual order. Use the explicit pin table above when wiring because output names and package pin numbers are different.

Reset and Pause the Sequence Deliberately

Hold pin 15 low for normal counting. A pull-down resistor and a reset switch to the positive rail can provide a manual reset, provided the input remains within its supply limits. Holding reset high selects Q0 regardless of the clock.

For a predictable first state, pause counting, assert reset, release reset, then resume the clock at a defined point. Releasing reset during a running clock can make the first displayed dwell shorter than subsequent complete periods.

Pin 13 is clock inhibit, not serial data. Keeping it low enables normal rising-edge counting. Holding it high prevents advancement through the normal clock input while preserving the current count.

For a clean pause-and-resume feature, control inhibit with attention to the clock state and datasheet timing. Changing it arbitrarily near a clock transition can make the first resumed step ambiguous. A mechanical switch may need debouncing or synchronized control for reliable behavior.

Do not assume a real counter always powers up at Q0 just because a simulator does. Provide a reset strategy if the initial display position matters. A reset supervisor is more reliable across different supply ramps than an unexamined RC power-on pulse.

Measure Pattern Timing

With the calculated 0.1012 s clock period, a complete ten-state sequence takes approximately 1.012 s. Reducing the clock frequency by half doubles both the position dwell and complete sequence time.

The endpoint LEDs occur once per ten-state cycle, while each interior LED occurs twice. Consequently, an interior LED has twice the total on-time per complete cycle, although each individual visit lasts one clock period. This can affect perceived brightness when the pattern runs quickly.

If equal average brightness is required at high speed, the sequence or drive strategy needs adjustment. Do not confuse that visual integration effect with a wrong resistor or defective LED.

Use an oscilloscope or logic analyzer to compare the clock with Q0 and another output. Q0 should recur once every ten clock periods. The carry-out signal also divides the clock rate by ten, but it is not an eleventh decoded position.

Design a Different Pattern on Paper First

To change the visual sequence, write one row for each counter state and list the LED that should illuminate. Check that every state has a defined purpose. Then group together the states that select the same LED and provide a separate isolation path from each corresponding output.

For example, a ten-position circular display can connect Q0 through Q9 to ten separate LED branches. It needs no paired-output mapping because each state has its own position. The same clock and counter can therefore create a very different visual effect without changing their basic operation.

A shorter back-and-forth display may need fewer than ten states. Four positions with no repeated endpoints require six states: first, second, third, fourth, third, second. A modulo-six counter sequence then needs a deliberately designed reset or state-control arrangement. Do not simply leave four outputs unconnected and expect the cycle to shorten; those states would become dark intervals.

When a decoded output is used to reset a counter early, the feedback creates a short reset event. Check the reset pulse and device timing rather than assuming any arbitrarily brief glitch is acceptable. The output used to initiate reset should not also be treated as a full-duration display state.

Separate visible speed from electrical edge quality

A slow LED pattern can still depend on fast, clean electrical transitions. The clock period might be a tenth of a second while its rising edge occurs over a much shorter interval. Noise near the input threshold can produce extra transitions if the signal is poorly conditioned.

The CD4017 clock input has Schmitt-trigger action, but that does not make an unconnected input or a bouncing mechanical switch a reliable clock. Use the timer's defined output for the main demonstration and inspect suspicious edges on an appropriate time scale.

Keep a small measurement record containing supply voltage, clock period, clock high level and the sequence observed after reset. If the pattern occasionally skips, capture the clock and reset together. A reset disturbance can resemble a missing count when only the LEDs are observed.

Finally, remember that the timing capacitor and resistors have tolerances. A nominal 9.88 Hz oscillator may run somewhat faster or slower on hardware. That changes the animation speed but should not change the state order. If the order changes, investigate logic, reset or wiring rather than trying to recalibrate the timing resistor.

Simulation, Download and Troubleshooting

Build and test the clock first, then add the counter without the LED mapping. Once the decoded sequence is correct, add one diode-isolated LED path at a time. This makes a wrong diode or output connection easier to locate.

The original archive is preserved below. Its historical resistor-combined outputs have not been replaced with the revised diode network, so make those changes deliberately before using it as a hardware reference.

Download Sequential LED Blinking Project Using 555 Timer

The design review should answer four questions: Is the clock electrically valid? Does the counter advance through its ten states? Does the output map select the intended LED? Is every current path limited and isolated? Answering them separately avoids treating every fault as a timer problem.

Frequently Asked Questions

Is the CD4017 a ten-bit shift register?

No. It is a decade counter with ten decoded outputs. This circuit has no arbitrary serial data stream.

Does the counter reverse direction?

No. It counts forward. The LED mapping creates the appearance of reverse motion.

Can I connect Q1 and Q9 together?

Do not directly tie the active outputs together. Use an appropriate isolation or logic network, such as the diode arrangement described here.

Why do six LEDs use ten states?

The pattern visits both endpoints once and the four interior positions twice during each round trip.

Can I change the speed without changing the sequence?

Yes. Adjust the clock timing while keeping valid signal levels and pulse widths. The counter-to-LED mapping remains the same.