Chiplet-Based Design: How Advanced Packaging Is Changing PCB Architecture

For decades, electronic systems have been built around a relatively clear hierarchy. Transistors form an integrated circuit, the integrated circuit is enclosed in a package, and the package is mounted on a printed circuit board. The PCB then connects processors, memory, communication devices, power converters, sensors, and external interfaces into a complete product.

Chiplet-based design is making that hierarchy less distinct. Instead of placing every major function inside one large monolithic system-on-chip, engineers can divide the system into smaller semiconductor dies called chiplets. These dies may be manufactured with different process technologies and then connected inside an advanced package. The result behaves like a highly integrated device, even though it contains several separate pieces of silicon.

This development does not make the PCB obsolete. It changes what the PCB must do. Some connections that previously crossed the board are moving into package substrates, redistribution layers, bridges, and interposers. At the same time, the PCB must supply more current, control faster external interfaces, remove concentrated heat, and accommodate packages with very high pin counts. Chiplet technology is therefore changing PCB architecture from both directions: more integration occurs inside the package, while the board supporting that package becomes more demanding.

What Is a Chiplet?

A chiplet is a small semiconductor die designed to perform a particular function as part of a larger system. One chiplet might contain processor cores, while others provide graphics acceleration, artificial-intelligence processing, memory interfaces, input/output functions, radio-frequency circuitry, or security features.

In a conventional monolithic system-on-chip, these functions are fabricated together on one die. That approach provides short internal connections, but it becomes expensive and difficult as the die grows. A large die is also more vulnerable to manufacturing defects because one defective region can cause the entire device to be rejected.

Chiplet architecture breaks the design into smaller functional blocks. This gives semiconductor companies several important options:

• A compute chiplet can use an advanced manufacturing node, while less performance-sensitive I/O can use a mature and less expensive node.

• Proven chiplets can be reused across multiple products.

• Memory, analog, RF, and digital technologies can be combined without forcing every circuit onto the same semiconductor process.

• Smaller dies can potentially improve manufacturing yield compared with one very large die.

• Product families can be created by changing the number or combination of chiplets.

The concept is modular, but chiplets are not equivalent to ordinary PCB modules. Their interconnections are extremely short, dense, and fast. They are assembled within the same package rather than being distributed across a conventional circuit board.

Why Advanced Packaging Is Essential

Separating a processor into smaller dies creates a new problem: those dies must communicate almost as efficiently as circuits on a single piece of silicon. Sending every connection through a standard package and across a PCB would add too much distance, capacitance, power consumption, and latency.

Advanced packaging provides the missing interconnection layer. According to imec's overview of chiplet integration, the two major approaches are 2.5D integration, in which dies are positioned side by side and connected through an interposer, and 3D integration, in which dies are stacked vertically.

2.5D Integration

In a 2.5D structure, multiple dies are placed beside one another on a shared interposer or other high-density routing layer. The interposer provides much finer conductors than a normal PCB and supports a large number of short die-to-die connections.

Silicon interposers can offer extremely fine routing, controlled electrical characteristics, and dense vertical connections through through-silicon vias. Organic interposers and advanced package substrates may offer a more economical alternative for designs that do not need the finest geometry. Local silicon bridges can also connect only the edges of neighboring dies, reducing the amount of silicon used for the interconnect structure.

3D Integration

In 3D integration, dies are placed on top of one another. Vertical stacking can shorten connections even further and reduce the package footprint. It is particularly attractive for combining logic and high-bandwidth memory.

However, stacking increases thermal difficulty. Heat produced by a lower die must pass through other materials before reaching a heat spreader. Power delivery and mechanical stress also become harder to manage. A 3D package may save board area while demanding a more sophisticated thermal solution at the system level.

Fan-Out and Redistribution Layers

Fan-out packaging uses fine redistribution layers to route connections from closely spaced die pads to a larger area. It can support multiple dies without requiring a full silicon interposer. This approach occupies a middle ground between conventional packages and more expensive 2.5D integration.

The best packaging method depends on bandwidth, power, cost, thermal limits, manufacturing volume, and acceptable package size. In all cases, advanced packaging performs routing that would be impossible or inefficient on a standard PCB.

Working with PCBWay on Boards for Advanced Packages

Chiplet-based products still need a carefully engineered system PCB, particularly when a large BGA package must connect to high-speed interfaces, high-current power rails, and dense peripheral circuitry. For development teams, working with a manufacturer that supports HDI fabrication, controlled impedance, blind and buried vias, high-frequency materials, and multilayer construction can make the transition from layout to physical prototype more manageable.

PCBWay's advanced PCB capabilities include HDI structures with stacked or staggered microvias, impedance-controlled boards, high-frequency material options, rigid-flex construction, and multilayer fabrication. These processes are relevant to carrier and system boards that must escape fine-pitch packages while preserving power and signal integrity. PCBWay also provides PCB assembly and low-volume manufacturing services, allowing design teams to move from bare-board validation to assembled prototypes through the same supplier.

Early design review is particularly valuable for these projects. Before releasing the final Gerber, drill, and assembly data, engineers can confirm the proposed stackup, minimum trace and space, laser-via structure, copper weights, impedance targets, via-in-pad requirements, surface finish, and BGA assembly constraints with PCBWay. This manufacturer feedback can expose fabrication risks before they become failed boards, helping teams improve yield, control prototype costs, and prepare the design for later production.

Package Substrates Are Becoming More Like High-End PCBs

Package substrates and PCBs are still different products, but their design concerns increasingly overlap. Both use patterned copper, dielectric layers, plated connections, controlled impedance, and multilayer routing. The main differences are feature size, materials, fabrication processes, and the density of interconnections.

As chiplet packages gain more connections, their substrates require finer traces, smaller vias, more routing layers, and more precise registration. Technologies such as microvias, build-up layers, semi-additive copper processes, and low-loss dielectric materials are therefore becoming increasingly important. These developments resemble the progression from conventional multilayer PCBs to high-density interconnect boards, although advanced package substrates operate at significantly finer dimensions.

How Chiplets Change System-Level PCB Architecture

The most visible effect of chiplets is often a reduction in the number of large components around the main processor. Functions that once required separate packages may be integrated into one multi-die package. Yet this apparent simplification hides several new board-level challenges.

Fewer Board-Level Data Paths

Moving memory controllers, accelerators, and specialized I/O dies into the package shortens critical connections. Instead of routing wide parallel buses across several centimeters of PCB, designers can keep them within the package. This can reduce board area, the number of high-speed PCB layers, and some sources of electromagnetic interference.

The board is then used mainly for connections that must leave the package: power, storage, networking, peripheral interfaces, sensors, and connectors. This separation can simplify certain routes, but the remaining interfaces may still operate at very high speeds.

Larger and More Complex Package Footprints

A multi-chiplet package may have a large ball-grid array with thousands of connections. Escaping those connections can require high layer counts, fine traces, via-in-pad structures, blind and buried vias, or multiple HDI build-up cycles.

The land pattern cannot be treated as an isolated footprint. It has to be developed together with the stackup, via technology, breakout strategy, fabrication tolerances, and assembly process. Waiting until routing begins to discuss these constraints with the board manufacturer can lead to an expensive redesign.

More Demanding Power-Delivery Networks

High-performance chiplet packages can draw large, rapidly changing currents. Even when the average power is manageable, fast load transients can cause voltage droop and ground noise. The PCB power-delivery network must provide low impedance over a wide frequency range.

That typically requires:

1. Carefully designed power and ground plane pairs.

2. Short connections between voltage regulators and the package.

3. A hierarchy of bulk, mid-frequency, and high-frequency decoupling capacitors.

4. Sufficient copper and via capacity for high current.

5. Power-integrity simulation using realistic package and board models.

Some high-frequency decoupling may be placed inside the package because PCB-mounted capacitors are limited by mounting inductance. The PCB still handles lower-frequency energy storage and distributes power from the regulators to the package. Package and board power networks therefore need to be designed as one connected system.

Greater Thermal Concentration

Combining several active dies creates a concentrated heat source. The package may occupy less board area than the collection of components it replaces, but it can produce more heat per unit area.

PCB designers must consider copper spreading, thermal vias, airflow, heat-sink mounting, board thickness, component clearance, and possible liquid-cooling hardware. Temperature-sensitive components should be kept away from the main heat path. Mechanical designers also need accurate package-height, loading, and keep-out information for the heat sink or cold plate.

Thermal behavior becomes even more important with stacked dies because the heat sources are located at different depths. Board-level simulation should therefore use package-specific thermal models rather than treating the device as a uniform rectangular heat source.

Signal Integrity Moves from the PCB to the Complete Channel

Chiplets encourage engineers to analyze the complete electrical path rather than treating the die, package, and PCB as separate domains. A signal may travel through an on-die transmitter, a microbump, an interposer trace, package vias, solder balls, PCB traces, a connector, and another device.

Every transition introduces impedance discontinuity, loss, reflection, or crosstalk. The package may remove long PCB routes for internal die-to-die communication, but it also adds new interfaces that must be modeled accurately.

Designers should coordinate:

• Reference impedances across package and board structures.

• Return-current paths at every layer transition.

• Differential-pair geometry and skew.

• Via stubs and antipad dimensions.

• Package breakout routing and connector placement.

• Dielectric loss at the intended data rate.

• Simultaneous switching noise and power-supply coupling.

This encourages package-board co-design. Stackups, pin assignments, power domains, and escape routes should be evaluated before the package is finalized. In advanced systems, the PCB designer may need package S-parameters, IBIS models, power models, and thermal data much earlier than in a traditional workflow.

Standardization and the Open Chiplet Ecosystem

A modular chiplet market becomes far more useful if dies from different suppliers can communicate reliably. The UCIe Consortium defines an open die-to-die interconnect specification intended to support an interoperable chiplet ecosystem at the package level. Its specifications address areas such as physical connectivity, protocols, manageability, debugging, testing, and different package constructions.

Standardization could let system developers select compatible compute, memory, I/O, accelerator, and security dies in a manner that resembles selecting IP blocks. However, electrical compatibility alone is not sufficient. The ecosystem also needs shared approaches to mechanical footprints, thermal limits, known-good-die testing, security, reliability, and supply-chain traceability.

This is one reason chiplet design requires close cooperation among semiconductor foundries, packaging companies, EDA vendors, PCB manufacturers, assembly providers, and system designers. A failure at any boundary can affect the entire product.

Testing and Reliability Become System Problems

Testing a monolithic IC is already complex. Testing a package containing several chiplets, thousands of die-to-die links, and a dense PCB interface adds more potential failure points. The industry must verify bare dies, interconnections, package structures, solder joints, and board-level operation.

As board and package densities increase, conventional inspection methods may struggle to identify subtle defects efficiently. Manufacturers are therefore applying computer vision, machine learning, and predictive analytics to automated optical inspection, solder-joint analysis, equipment monitoring, and process optimization. These developments in AI-powered PCB quality control and assembly could become particularly valuable for chiplet-based systems, where fine-pitch BGAs, dense HDI routing, and limited physical access make early defect detection essential.

Known-good-die testing is essential because assembling a defective die into an expensive multi-die package wastes every other component in that package. After assembly, built-in self-test, boundary scan, link monitoring, and thermal sensors can help isolate failures. At the PCB level, designers should provide access for power-rail measurement, programming, debugging, and functional testing wherever package density permits.

Reliability analysis also has to consider mismatched coefficients of thermal expansion. Silicon, organic substrates, solder, underfill, and PCB laminate expand at different rates. Repeated heating and cooling can stress microbumps, package balls, vias, and the board itself. Warpage becomes a serious concern as package size increases, making land-pattern design, reflow profiling, underfill selection, and mechanical support important parts of system reliability.

A Practical Design Workflow for Chiplet-Based Systems

PCB teams preparing for advanced multi-die packages can follow a structured workflow:

1. Define the system partition. Decide which functions belong in the package and which remain as board-level components.

2. Model power and heat early. Estimate rail currents, transient behavior, package power density, cooling requirements, and regulator placement before fixing the board outline.

3. Develop the package and PCB together. Coordinate ball assignments, breakout directions, layer transitions, reference planes, and decoupling locations.

4. Confirm fabrication limits. Review stackup, microvias, aspect ratios, pad sizes, registration tolerances, and materials with the PCB manufacturer.

5. Simulate complete channels. Include die, interposer, package, PCB, and connector models for critical interfaces.

6. Plan assembly and inspection. Establish reflow limits, warpage controls, X-ray inspection criteria, rework restrictions, and handling procedures.

7. Design for test and telemetry. Include accessible measurement points and use built-in monitoring where physical probes cannot reach.

8. Validate with staged prototypes. Test power delivery, thermal behavior, signal integrity, and mechanical reliability before committing to volume production.

Challenges That Could Slow Adoption

Chiplets offer compelling flexibility, but they are not a universal replacement for monolithic devices. Advanced packaging can be costly, and the design requires specialized modeling, assembly, and test capabilities. Additional die-to-die interfaces consume power and can create latency compared with circuits located on the same silicon die.

Supply-chain coordination is another challenge. A multi-vendor package depends on compatible specifications, reliable die availability, shared quality standards, and clear responsibility when failures occur. Security also matters because chiplets may come from different suppliers and exchange sensitive data through standardized interfaces.

For lower-cost or low-volume products, a conventional processor and PCB may remain the better solution. Chiplet integration is most attractive when performance, modularity, product reuse, heterogeneous technologies, or scaling economics justify the packaging complexity.

The Future Relationship Between Chiplets and PCBs

The boundary between semiconductor packaging and PCB engineering will continue to shift. More high-bandwidth connections will move from the system board into the package, while the PCB will become the platform for delivering power, cooling, external connectivity, mechanical support, and serviceability.

This evolution may encourage wider use of HDI boards, low-loss laminates, embedded passive components, optical interconnects, and advanced cooling structures. PCB engineers will need a stronger understanding of package behavior, while package designers will need to consider board fabrication and assembly limits earlier in development.

Chiplet-based design should therefore be viewed not as the end of PCB architecture but as its next transformation. Advanced packaging brings semiconductor dies closer together, yet the success of the finished product still depends on the board beneath them. The strongest designs will come from treating the die, package, PCB, power system, and mechanical enclosure as one interconnected engineering problem.