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In system memory editor of Altera for Xilinx
Hi!,
I have been working with Altera FPGAs for a long time and now I have to
deal with Xilinx ones. Until now, with Quartus II I have been able to
ma ...
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Outlook question help and information.
11:33 PM
.txt file to xilinx FPGA
HI everyone.
i need to get an input (column of bits) from .txt file via usb into xilinx FPGA.
so if anyone can help me i will be grateful.
and thanks ...
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verilog code of sin wave generation
i need verilog code of sine wave generator........i tried with cordic algorithm but i cant able to proceed
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Doubt regarding using ODIN II tool for converting a verilog file into BLIF format
I am an M.tech student and have been working on a project related to FPGA architecture research.In this, among other things i am supposed to convert v ...
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128 data to show on LCD 32hex of spartan 3E
can anyone please help. i am trying to make a verilog code for 128bit data to show on LCD of spartan 3E.
but its just showing first line means 64 bit ...
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problem in vhdl test bench cod
hello,
Why the following testbench code in the first clock d1, d2 are value
And the second clock a, b
[code]library IEEE;
use ieee.std_logic_1164.all ...
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Zynq 7000 board required
Guyz,
Any one with zed board(zynq 7000 based) do give a reply. Trying to get this board for my research.
Thanks in advance.
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Digital Timer
Can anyone here give me the verilog code for a digital timer which includes a counter , finite state machine and display?
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Sending an Image file into an FPGA!
Hello guys, I am completely new with the device. I attempting to implement an image processing algorithm onto an fpga. I am trying to do this by expli ...
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Real data type increment by fraction in VHDL
Hi,
I am trying to increment real data by 0.03 in LOOP.Not able to see exact values.
angle <= angle + 0.03;
when angle is real data type.
in si ...
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Associate Engineer
Arduino Code Serial Communication
