An STM32 timer runs twice as fast as expected: which clock should be checked?

Determine the actual timer input clock for that timer instance and MCU family. It may differ from both the core clock and the peripheral bus frequency. Some configurations multiply the timer clock relative to a divided APB clock; check the device's clock-selection rules rather than assuming universal behavior.

For a simple edge-aligned up-counter, the update rate is f_timer / ((PSC + 1) × (ARR + 1)). With a verified 100 MHz timer input, PSC = 99 and ARR = 999 give 1 kHz. Center-aligned modes and other timer features require their own timing analysis.

Measure the output or interrupt marker and inspect the initialized registers. Check when buffered prescaler and reload changes take effect. Recompute the timing after any clock-tree change, and avoid treating a configuration-tool diagram as a substitute for confirming the actual runtime settings.