STM32H7 DMA buffer looks stale: when should cache coherency be investigated?

First confirm that the DMA can access the chosen memory region and that addresses and transfer sizes are correct. A valid CPU pointer does not guarantee DMA accessibility. Then consider whether CPU cache contents and memory contain different versions of the same buffer.

Define ownership during each transfer and follow the device's cache-maintenance guidance for direction, alignment and range. Cleaning and invalidating have different purposes. Invalidation of a cache line shared with unrelated dirty data can discard changes, so isolated, suitably aligned buffers matter.

Test with a changing pattern and inspect memory before and after each ownership transfer. Disabling cache temporarily may help diagnosis but is not automatically the best final design. Use a deliberate memory-region or maintenance strategy and retest under realistic interrupt and DMA load.