Can a PSOC Edge graphics demo share memory bandwidth with continuous inference?

Measure display updates, image copies, preprocessing and inference separately, then together. Record where each buffer resides and which masters access it. Independent demonstrations can hide contention that appears only when display, CPU and accelerator traffic overlap.

A 480 × 272 frame at 16 bits per pixel contains 261,120 bytes. Rewriting it 30 times per second moves about 7.83 MB/s before scanout reads, extra copies or model traffic. This is an illustrative minimum for that operation, not a measurement of the board's total bandwidth.

Consider smaller update regions, fewer copies and deliberate buffer lifetimes where the hardware and graphics stack support them. Verify visual correctness and inference accuracy after changes. Report worst-case frame delay and result latency under the combined workload rather than separate peak rates.