Does enabling compressed RISC-V instructions always make firmware faster?

Compressed encodings can reduce instruction storage and fetch demand for eligible operations, but they do not make every operation execute in fewer cycles. Confirm that the chosen core and compiler configuration support the relevant extensions and keep the optimization level consistent between comparisons.

Measure the actual workload from its deployed memory location. Flash wait states, instruction-fetch behavior, branch patterns and alignment can influence timing. A tiny loop running from RAM may not reflect a larger application executing from external or slower memory.

Compare text size, peak stack use and worst-case timing with identical inputs. Inspect disassembly to understand a surprising result instead of inferring speed from binary size. Keep the smaller build if it meets the timing requirement, even when the main benefit is memory rather than CPU time.