Ethernet MAC vs PHY: what does each do, and what connects them (MII, RMII, RGMII)?

The MAC (media access controller) is the digital half. It builds and checks frames: preamble, destination and source addresses, length or type, payload and the 32-bit frame check sequence, and it filters incoming frames by address and handles flow control. It knows nothing about voltages on the cable. The PHY is the mixed-signal half: it turns the MAC's bits into the line signal for the particular medium and back, recovers the clock from the incoming signal, detects the link and negotiates speed and duplex with the partner.

For 100BASE-TX, for example, the PHY encodes each 4 bits as a 5-bit code (4B5B), giving 125 million symbols per second, scrambles them and sends them as a three-level MLT-3 signal. The MAC just sees 100 Mbit/s of data.

They are separate because they are different kinds of circuit. The MAC is pure logic and fits naturally into a microcontroller or FPGA. The PHY contains line drivers, adaptive equalisers and analog-to-digital conversion, which need more supply current and analog design, and the right PHY depends on the medium: copper at 10/100, gigabit copper, fibre, single-pair automotive. Keeping a standard interface between the two lets one MAC design work with any of them.

Single-chip combinations exist where the market is large enough. The ENC28J60 is a MAC plus 10BASE-T PHY behind an SPI port, and the W5500 adds a hardwired TCP/IP stack on top of a 10/100 MAC and PHY, which is why it needs only the magnetics and connector.

The interfaces between MAC and PHY differ in pin count and clocking. MII moves 4 bits at a time in each direction with 25 MHz clocks for 100 Mbit/s (4 × 25 MHz), using 16 signals. RMII halves the width to 2 bits and doubles the clock to a single shared 50 MHz reference (2 × 50 MHz), cutting the interface to 7 signals: two transmit data, transmit enable, two receive data, a combined carrier-sense and data-valid line, and the clock. RGMII serves gigabit with 4 data bits per direction clocked on both edges of a 125 MHz clock (4 × 2 × 125 MHz = 1000 Mbit/s) over 12 signals.

Most microcontrollers with a MAC use RMII because of the pin saving. Its one demand is the 50 MHz reference clock, which both MAC and PHY must receive from the same source.

MDIO and MDC form the separate management bus, a slow two-wire serial link that the MAC side uses to read and write the PHY's registers. Up to 32 PHYs can share it, each with a 5-bit address set by strap pins at reset. The first registers are standardised: register 0 is basic control (reset, auto-negotiation enable, speed, duplex), register 1 is basic status, including the link bit, and registers 2 and 3 hold the PHY identifier.

Reading registers 2 and 3 is the standard first test of a new board: if you get the ID from the datasheet, the management bus, the address strap and the PHY's clock and reset are all working. MDIO needs a pull-up resistor, commonly 1.5 kΩ, and a wrong PHY address in the driver is a very common reason for a board that reports no PHY or no link.

One thing these chips usually do not give you is the MAC address itself. Most microcontroller MACs and the W5500 come without a factory-programmed address, so the firmware must load one at start-up. For products, buy an address block or use a small EEPROM that comes pre-programmed with a globally unique address. For lab work, use a locally administered address: in the first byte, bit 1 set and bit 0 clear, which means the second hex digit is 2, 6, A or E, for example 02:00:00:12:34:56.

Every device on a network needs a different address. Two boards flashed with the same example code and the same address will each appear to work alone and fail in confusing ways together.