FPGA simulation works but hardware fails after reset: where should reset release be checked?

Check how reset is released in each clock domain and whether the relevant clocks are stable and running. An asynchronous release can violate recovery or removal timing. Use an appropriate, reviewed reset strategy for the device and each domain.

Identify dependencies between state machines, FIFOs and external interfaces. One domain may begin sending before another is ready. Use explicit readiness or handshake conditions where needed, rather than assuming all reset synchronizers release on the same global instant.

Vary reset timing relative to clocks in simulation and test repeated resets on hardware. Capture the first invalid transition with internal debug instrumentation. Also review whether a stopped clock prevents the selected release circuit from completing, which a normal startup simulation may never exercise.