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I2C, SPI, UART & RS-485 DISCUSSION
My ATmega328P runs from a 16 MHz crystal and talks to a module at 115200 baud. It mostly works, but I get occasional corrupted bytes that disappear at 57600. The baud rate calculator shows an error of a few percent at 115200.
How much difference between the two ends is acceptable, and why does it matter if the crystal itself is accurate?
The receiver resynchronises on every start bit and then samples each bit near its centre using its own clock. The timing error accumulates across the frame. With 8N1 the last sample that matters is the stop bit, about 9.5 bit periods after the start edge. That sample must still fall inside the correct bit, so the accumulated drift has to stay under half a bit: 0.5 / 9.5 is about 5 percent of total mismatch between transmitter and receiver in the ideal case.
In practice the budget is smaller. The receiver finds the start edge with its oversampling clock, usually 16x, so there is already up to 1/16 bit of uncertainty, and slow edges take away more. A common working rule is to keep each end within about ±2 percent, so that the combined error stays clear of the limit.
The crystal is accurate, but the baud rate generator can only divide by whole numbers. On the AVR in normal mode the divisor is F_CPU / (16 × baud) - 1. For 16 MHz and 115200 that is 7.68, which rounds to 8 and gives 16,000,000 / (16 × 9) = 111,111 baud, an error of about -3.5 percent. That is right at the edge, which matches occasional bad bytes.
With the double-speed bit (U2X) set, the divisor is 16 and the rate is 117,647 baud, about +2.1 percent. At 57600 the error is about +2.1 percent in normal mode and -0.8 percent with U2X, and 38400 in normal mode is only 0.2 percent off.
If both ends must be exact, change the clock rather than the settings. Crystals such as 7.3728 MHz, 11.0592 MHz, 14.7456 MHz or 18.432 MHz divide to the standard baud rates with zero error, which is why they exist.
Also check which way the other end is off. If the module is at +1.5 percent and you are at -3.5 percent, the total is 5 percent and it will fail, while the same module against +2.1 percent is comfortable.
To confirm the diagnosis, send a continuous stream of 0x55 and measure one bit width on a scope or logic analyser; 115200 baud should be 8.68 µs per bit. If the errors only appear in long back-to-back bursts and not in single bytes, that also points to accumulated timing error, and adding a second stop bit on the transmitter gives the receiver more room to resynchronise.
