Pico PIO output has occasional gaps: can DMA still leave the FIFO empty?

DMA reduces CPU involvement but does not create an unlimited source of data. Check the PIO program's blocking pull behavior, FIFO depth and the DMA request selection. Use the correct peripheral DREQ to pace transfers; an inappropriate request source can break the expected producer-consumer timing.

Compute the consumption rate from the actual instruction sequence and clock divider, including delay fields and loops. If the state machine consumes one 32-bit word every 2 µs, it needs 500,000 words per second, or 2 MB/s. That rate must remain available during buffer transitions as well as steady transfer.

Capture the gap and a marker for buffer handover with a logic analyzer. Inspect transfer counts, chaining and which code refills the next buffer. Provide explicit underrun detection and a defined safe output state rather than silently replaying stale data when the producer falls behind.