RA clock changes affect UART and timers differently: how can the configuration be checked?

Trace the actual clock source and divider for each peripheral on the chosen RA part. Different bus or peripheral clocks can respond differently to a system-clock change. Review the generated FSP clock configuration and the driver's assumptions about runtime changes.

Compute the intended timer period and UART divider from their own input clocks, including hardware rounding. For UART, compare actual baud with the target using error = (actual - target) / target × 100%. The acceptable combined transmitter and receiver error depends on the link and frame format.

Measure a timer output and serial waveform before and after the transition. Reinitialize or update peripherals through the supported sequence when required. Test an active transfer during the transition so a correct steady-state configuration does not hide a one-time communication fault.