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RISC-V Microcontrollers DISCUSSION
A portable library uses atomic operations, but a small RISC-V MCU implements fewer extensions than the original target. What should be checked to understand whether those operations remain correct and appropriate for interrupt use?
Reference: GCC: RISC-V target options (https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html).
Verify the target ISA, compiler support and how each atomic operation is lowered. Do not assume that every RISC-V MCU provides the same hardware atomic instructions. Some operations may require library routines, and their implementation affects timing and allowed execution contexts.
Check whether the required operation is lock-free on the actual type and target. A library helper that uses a lock can be unsuitable when an interrupt preempts code holding that lock. For a single-core MCU, a carefully bounded interrupt-masking strategy may be appropriate for some shared state, subject to latency requirements.
Document memory-ordering requirements and test the real producer-consumer paths. Volatile does not replace atomicity or synchronization. Keep the chosen strategy specific to the platform, particularly when moving from a single-core device to a multicore system with different shared-memory behavior.
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