Routing USB 2.0 D+ and D- on a two-layer PCB: how much does 90 ohm impedance matter?

Impedance control matters when the trace is long compared with the signal's edge. Full-speed USB (12 Mbit/s) has rise and fall times specified between 4 and 20 ns. Signals travel along FR-4 traces at roughly 150 mm per ns, so even the fastest 4 ns edge is about 600 mm long. A common rule treats a trace as a transmission line only when it is longer than about one sixth of that, 100 mm here. Your 25 mm connection is electrically short: reflections settle within the edge, and the exact impedance has little effect.

High-speed USB (480 Mbit/s) is a different matter. Its edges are around 500 ps, the same rule gives roughly 12 mm, and there the 90 Ω requirement must be taken seriously.

The calculator is right about two-layer boards. Differential impedance depends on trace width, spacing and the distance to the reference plane. With 1.6 mm between the traces and the ground on the other side, a 90 Ω pair needs very wide traces or a very tight gap, which is why the result looks absurd. On a four-layer board the plane is only about 0.1 to 0.2 mm below the surface and the same impedance comes out at comfortable widths.

For a short full-speed link on two layers, route the pair with ordinary trace widths, side by side with a constant gap, and accept that the impedance is higher than nominal. For high-speed USB, move to four layers or use a coplanar structure with ground beside the traces, and take the dimensions from your manufacturer's impedance calculator for their actual stackup.

The rules that matter at any speed: keep D+ and D- together as a pair from connector to chip, over unbroken ground copper on the other layer for the whole route. Do not let the pair cross a gap or slot in the ground, because the return current then has to detour and the loop radiates and picks up noise. Avoid vias in the pair if you can; if you need them, move both traces through vias at the same point and add a ground via next to them. Avoid stubs, such as a test point hanging on a side branch.

Keep the pair away from switching regulators, crystals and clock lines, and place the ESD protection device right at the connector so a discharge is diverted before it travels along the board.

Length matching is often overdone. Delay on FR-4 is about 6 to 7 ps per millimetre, so a 5 mm mismatch between D+ and D- is roughly 33 ps of skew. A full-speed bit lasts 83.3 ns, so that skew is 0.04 % of a bit and completely irrelevant. Even at high speed the bit is 2.08 ns and 33 ps is under 2 %; PHY layout guides typically ask for matching within a millimetre or two, which is easy to meet on a short route without serpentine tuning. Do not add meanders to a full-speed pair; they only make the route longer.

With USB-C there is one unavoidable asymmetry: the connector has two D+ and two D- pins that must be joined, which creates a small stub or crossing. Keep those joining traces as short as possible, directly at the connector pads.