SPI reads return shifted or garbage bits: how do I work out the correct SPI mode?

A value shifted by one bit is the classic sign of a wrong clock phase. The four modes come from two settings. CPOL is the idle level of the clock: 0 idles low, 1 idles high. CPHA selects the sampling edge: 0 samples on the first edge after chip select goes active, 1 samples on the second edge.

So mode 0 (CPOL 0, CPHA 0) samples on the rising edge, mode 1 (0, 1) on the falling edge, mode 2 (1, 0) on the falling edge and mode 3 (1, 1) on the rising edge.

To read it off a timing diagram, look at two things. First, the level of SCK while chip select is high or just as it falls: that is CPOL. Second, find where the data lines are shown stable, usually with a setup and hold time marked around one clock edge: that edge is the sampling edge. Data changes on the opposite edge.

Many sensors state that they accept both mode 0 and mode 3. Those two sample on the same rising edge and differ only in the idle level.

Other settings give similar symptoms, so check them as well. Bit order must match; nearly all sensors are MSB first. Many devices use the top bit of the first byte as the read/write flag, so reading register 0xD0 may require sending 0xD0 with bit 7 set or cleared depending on the part. Chip select must stay low for the whole transaction, address byte and data bytes together; if the driver raises it between bytes, the device restarts and the reply is meaningless.

If the mode is right and the bits are still unreliable, slow the clock down. Long jumper wires add capacitance and ringing, and a device's maximum SPI clock is often lower for reads than for writes. Try 100 kHz first, confirm the ID, then raise the rate.

A logic analyser with an SPI decoder settles this quickly: capture SCK, MOSI, MISO and CS, set the decoder to each mode, and the one that decodes 0x58 is the mode the device is actually using.