English is currently available.
VHDL DISCUSSION
My multiplexer process is declared process(a, b) and contains if sel = '0' then y <= a; else y <= b; end if;. In simulation y does not change when only sel changes, but the synthesised design on the board switches correctly, and the tool printed a warning about sel being read but missing from the sensitivity list. For clocked processes I have seen both process(clk) and process(clk, rst).
What are the rules for the sensitivity list in combinational and clocked processes?
The sensitivity list is an instruction to the simulator: run this process again whenever one of these signals has an event. With process(a, b), a change on sel alone does not wake the process, so y keeps its old value in simulation until a or b next changes.
Synthesis works from the statements inside the process, sees a two-input multiplexer and builds one, ignoring the list apart from the warning. The hardware is right and the simulation is wrong, and a simulation that does not match the hardware is of no use for verification.
For a combinational process the rule is: every signal that is read anywhere in the process must be listed. That means signals on the right-hand side of assignments, in if and case conditions, and used as indexes. Here that is process(a, b, sel). Signals that are only assigned do not belong in the list.
With VHDL-2008 you can write process(all), which means exactly that and cannot go stale when the code is edited. It is supported by current simulators and the main synthesis tools, though you may need to select the 2008 language version in the project settings.
For a clocked process the list is shorter. With a synchronous reset, or none, only the clock is needed: process(clk) with everything inside if rising_edge(clk) then. Nothing can change except on a clock event, so no other signal needs to wake the process, however many are read inside. With an asynchronous reset, the reset must wake the process as well: process(clk, rst) with if rst = '1' then ... elsif rising_edge(clk) then ... end if;.
Adding data signals to the list of a clocked process does not change the hardware; it only makes the simulator run the process more often for no effect.
Some background that makes the rules less arbitrary. A process with a sensitivity list is equivalent to the same process with a wait on statement for those signals as its last statement; you may use one style or the other, not both. Every process also runs once at the start of simulation regardless of events, which is why an incomplete list often looks correct at time zero and only fails later.
The opposite mistake, a combinational process that does not assign its output on every path, is a different problem: that infers a latch in hardware. Give each output a default assignment at the top of the process to avoid it.
Back to VHDL community
