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VHDL DISCUSSION
Older VHDL books write clocked processes as if clk'event and clk = '1' then, newer code uses if rising_edge(clk) then. Both synthesise to the same flip-flops in my 50 MHz design. In simulation, however, I noticed that the old form produced a clock edge at the very start, when clk went from 'U' to '1'.
Is rising_edge just shorthand, or does it behave differently? And can I use it on signals other than the clock, for example to detect a button press?
It is not just shorthand. clk'event and clk = '1' is true whenever the signal changes and its new value is '1', whatever it was before. rising_edge(clk) additionally requires the previous value to have been a low level. So a transition from 'U' or 'X' to '1' counts as a clock edge for the old form and not for rising_edge.
That is the extra edge you saw at time zero: the signal left its uninitialised state, and the old expression clocked every register in the design on it.
The function also handles the weak values of std_logic. It converts both the current and the previous value before comparing, so 'L' counts as low and 'H' as high. A clock modelled with a pull-up that goes from '0' to 'H' is a rising edge for rising_edge, whereas clk = '1' is simply false for 'H' and the old form misses every edge.
For synthesis the two are identical, since real logic has only 0 and 1. The difference is entirely in simulation accuracy, and there rising_edge and falling_edge are the better choice for all new code.
Keep clocked processes to one of two shapes that every tool recognises. Synchronous reset: process(clk) begin if rising_edge(clk) then if rst = '1' then q <= '0'; else q <= d; end if; end if; end process;. Asynchronous reset: process(clk, rst) begin if rst = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;.
Avoid variations such as an else branch after the edge test, which describe no real flip-flop. For a clock enable, nest a plain if en = '1' then inside the edge test; combining it as rising_edge(clk) and en = '1' is accepted by many tools but not guaranteed by all.
Do not use rising_edge on ordinary signals in a design meant for an FPGA. It would compile, but it turns that signal into a clock: the registers it drives sit in their own clock domain, fed over general routing with poor skew, and a bouncing button would clock them many times per press.
Detect edges synchronously instead. Pass the button through two flip-flops to synchronise it to the system clock, keep the previous sample, and compare inside the clocked process: btn_d <= btn_s; if btn_s = '1' and btn_d = '0' then pulse <= '1'; else pulse <= '0'; end if;. The result is a pulse exactly one clock period long, 20 ns at 50 MHz. A mechanical switch also needs debouncing, for example by requiring the input to be stable for 10 ms, which is a count of 500,000 cycles at that clock.
