Altium's current Constraint Manager documentation notes a distinction between preferred trace width and the minimum and maximum limits when an impedance profile is refreshed.
If a fabricator changes the dielectric thickness and the calculated preferred width changes, what should be reviewed before routing continues? How can we check that the board is using the intended constraint rather than an older inherited value?
Reference: Altium: Constraint Manager (https://www.altium.com/documentation/altium-designer/sch-pcb/constraint-manager).




