A two-flop synchronizer is present: why can an FPGA still lose a pulse?

A synchronizer reduces the probability that metastability propagates into downstream logic; it does not guarantee that a short pulse overlaps a destination sampling edge. Compare the source pulse width and event spacing with the destination clock period.

Choose an event-transfer scheme appropriate to the rate, such as a supported pulse synchronizer, toggle protocol or request-acknowledge handshake. Each has assumptions about spacing, reset and how many events can be outstanding. If every event must be preserved at higher rates, a suitable queue may be needed.

Use the vendor's recognized CDC structures where appropriate and review the CDC report. Simulate different phase relationships and burst patterns, then check constraints and reset behavior. A clean functional simulation with one convenient clock phase does not prove the crossing is reliable.