How do I choose CAN bit timing values (prescaler, segments, sample point, SJW) for 500 kbit/s?

A CAN bit is divided into time quanta (tq). The prescaler sets the quantum: tq = prescaler / f_clock. The bit is built from a synchronisation segment, always 1 tq, then segment 1 (propagation plus phase segment 1) and segment 2 (phase segment 2). The bus is sampled at the boundary between segment 1 and segment 2.

With 8 MHz and a prescaler of 1, tq = 125 ns. A 500 kbit/s bit lasts 2 µs, which is 16 tq. Choosing segment 1 = 13 and segment 2 = 2 gives 1 + 13 + 2 = 16 tq, and the sample point is at (1 + 13) / 16 = 87.5 percent of the bit.

The combinations from the calculator differ in the number of quanta and in the sample point. More quanta per bit give finer adjustment, so 16 tq is better than 8 tq where the clock allows it. For the sample point, a late position leaves more time for the signal to propagate and settle; 87.5 percent is the value recommended by CANopen and used by many devices, and values between about 75 and 87.5 percent are typical.

All nodes must agree on the bit rate, and they work best with similar sample points. If your first attempt sampled at, say, 62.5 percent while the other device assumes 87.5 percent, occasional errors are a plausible result, especially with some cable between them.

SJW, the synchronisation jump width, is how far the controller may lengthen or shorten a bit to stay aligned. Every node resynchronises on recessive-to-dominant edges; if the edge arrives early or late relative to its own sync segment, it adjusts phase segment 1 or 2 by up to SJW quanta. The range is 1 to 4 tq and it may not exceed phase segment 2.

A larger SJW tolerates more oscillator difference between nodes, so setting it as large as segment 2 allows is a common recommendation. Use a crystal on every node; internal RC oscillators are generally not accurate enough for CAN without calibration.

Cable length enters through the propagation segment. During arbitration and the ACK slot, a bit must travel from one node to the farthest node and the response must come back before the sample point. With about 5 ns/m, a 40 m bus has 200 ns of cable delay one way; add the loop delay of the transceiver at each end, roughly 100 to 250 ns each depending on the part, and the round trip is in the region of 600 to 900 ns. That has to fit before the sample point of a 1 µs bit, which is why 1 Mbit/s is limited to about 40 m.

Commonly quoted limits are about 100 m at 500 kbit/s, 250 m at 250 kbit/s and 500 m at 125 kbit/s. At 500 kbit/s with an 87.5 percent sample point you have 1.75 µs before sampling, ample for a few metres of cable.

Verify the result rather than trusting the arithmetic. Send a frame continuously and measure the width of a single bit with a scope: 2.00 µs for 500 kbit/s. A common mistake is using the wrong clock in the calculation, for example assuming the CPU clock when the CAN peripheral runs from a divided bus clock, which gives a bit rate off by a factor of two.

Also read how your driver numbers the fields: some registers store the value minus one, so a segment of 13 tq is written as 12. And check that the chosen prescaler gives exactly 500 kbit/s; the tolerance between nodes is well under 1 percent in practice.