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CAN & CANopen DISCUSSION
I understand that two CAN nodes can start transmitting at the same moment and that "the lower identifier wins" without the frame being destroyed. What I cannot picture is how that works electrically: on other buses two drivers talking at once simply corrupt the data.
What do dominant and recessive actually mean here, and what happens to the node that loses? Also, what if two nodes send the same ID at the same time?
The bus behaves like a wired-AND. A recessive bit (logic 1) is the undriven state: the terminators hold the two lines at the same voltage. A dominant bit (logic 0) is actively driven. If any node drives dominant, the bus is dominant, no matter how many others are sending recessive. Nothing fights, because a node sending recessive is not driving at all.
Every transmitter also reads the bus back while it sends. During the identifier field, a node that sends recessive but reads dominant knows that another node is sending a frame with a 0 at that position. It stops transmitting immediately and becomes a receiver.
Work an example. Identifiers are sent most significant bit first. Node A sends 0x65A = 110 0101 1010 and node B sends 0x653 = 110 0101 0011. The first seven bits are identical, so both continue. At the eighth bit A sends 1 (recessive) and B sends 0 (dominant). The bus shows 0. A sees the mismatch and drops out; B never notices that anything happened, and its frame continues undisturbed.
Since 0 beats 1 at the first differing bit, the numerically lower identifier always wins, which is why the ID is also the message priority.
The loser does not lose its message. It waits until the bus is idle again, after the end of frame and the intermission, and retries automatically; the controller does this in hardware. The cost is delay, not data.
That has a design consequence. If high-priority frames are sent back to back, low-priority ones can be delayed indefinitely, so IDs should be assigned by urgency and the bus should not be run near full load. Keeping the average bus load below about 50 percent is a common design target. The mechanism is called non-destructive bitwise arbitration, or CSMA/CR.
Two nodes sending the same identifier at the same time is a design error for data frames. Arbitration ends in a tie, both keep transmitting, and at the first bit where their data differs one of them sees a bit error and raises an error frame. Both retry, collide again, and their error counters climb. So each data frame ID must belong to exactly one transmitter.
Extended 29-bit frames follow the same rules. When a standard frame and an extended frame share the same first 11 bits, the standard frame wins, because its IDE bit is dominant where the extended frame sends a recessive one.
