11 Level 3-phase Cascaded H Bridge Inverter

Hello friends! Today, we will study an 11-level, three-phase cascaded H-bridge inverter in MATLAB and Simulink. We will begin with one H-bridge cell, connect five cells in series to form a phase, and then combine three phase assemblies. This approach makes the voltage levels easier to understand than starting with a large diagram full of switching signals.

The original project illustrates the overall arrangement and retains useful phase and line-voltage plots. We will keep those images while correcting the distinction between gate signals and power sources, the switching requirements for eleven levels, and the meaning of the older switch-model parameters. These details determine whether a simulation represents the intended converter.

Our emphasis is a transparent simulation model. We will calculate available voltage levels and provide a small ideal-waveform example, then discuss the additional work required for semiconductor switching, source balancing and practical operation. The original plots are historical examples, not measurements of a newly rebuilt inverter.

What Is a Cascaded H-Bridge Inverter?

An H-bridge has two switching legs connected across a DC source. Its AC output is measured between the two leg midpoints. Appropriate switch combinations can apply a positive source voltage, zero voltage or a negative source voltage to that output.

A cascaded H-bridge, often abbreviated CHB, connects several of these AC outputs in series. Their instantaneous voltages add. With equal source voltages, the converter can create a staircase of evenly spaced levels rather than only a positive and negative full-scale voltage.

The conventional arrangement uses electrically isolated or appropriately floating DC supplies for the individual cells. Do not connect all cell negative terminals together merely because each drawing contains a DC-source symbol. That can destroy the intended isolation and create unwanted current paths through the series-connected bridges.

Special single-source and capacitor-assisted variants exist, but they require additional power-conversion or balancing arrangements. They are not obtained by replacing every independent source in a conventional CHB with an arbitrary capacitor. Research on single-source CHB capacitor-voltage regulation addresses that additional control problem.

Why Five Cells Produce Eleven Phase Levels

For N equal-voltage cells, each able to produce −V_dc, zero or +V_dc, the available phase-string levels run from −NV_dc to +NV_dc in steps of V_dc. There are therefore 2N + 1 possible levels.

Setting 2N + 1 = 11 gives N = 5. One phase requires five full bridges and five DC links. A conventional three-phase system therefore contains fifteen cells and sixty controlled semiconductor positions, because each full bridge has four switches.

These values are an explanatory example, not a confirmed source setting from the old model. They also describe available states. A particular modulation depth may use only some levels during a cycle. Counting levels requires inspecting the actual waveform and control sequence.

Interpret the Original Top-Level Diagram

The historical top-level model groups the circuit into three phase subsystems. Inputs labeled pulse1, pulse2 and so on are control signals. They are not thirty DC power supplies. A gate signal tells a switch model what state to enter; a DC source provides electrical energy.

The number of independent control inputs depends on how the switching logic is packaged. Complementary signals or grouped commands can reduce the visible input count, but the underlying switch positions still need valid control. A block with ten visible inputs does not automatically prove that every required switching state has been implemented.

The internal image shows five bridge cells in a phase assembly. Each cell has a local source and four switch symbols, while the AC terminals are connected to form the phase string.

Trace the series path from the string's reference terminal to its phase output. Then inspect one cell at a time. This is more reliable than assuming the large subsystem is correct because its name says 11-level inverter.

Define a Valid H-Bridge Switching Table

Label the upper-left switch S1, lower-left S2, upper-right S3 and lower-right S4. Define positive cell voltage as the left midpoint voltage minus the right midpoint voltage. With ideal switches, the following commanded states produce the desired cell voltages.

Never turn on both devices in the same leg together. S1 with S2, or S3 with S4, directly shorts that cell's DC source in the ideal model. Hardware requires suitable interlocking and dead time during transitions; a Boolean complement alone does not account for device turn-off delay.

This also reveals an important limitation of diagonal-only control. If every cell is allowed only +Vdc or −Vdc, five equal cells produce sums of −5, −3, −1, +1, +3 or +5 times Vdc: six possible levels, not eleven. Controlled zero states are needed to obtain all integer steps.

Turning all switches off is not a general substitute for an actively selected zero state. With inductive current, antiparallel diodes can determine the cell voltage. Therefore, inspect the gate mapping and current paths in the original model before accepting its level count.

Understand the Historical Switch Parameters

The original parameter dialog is labeled IGBT/Diode and describes an idealized controlled-switch model with an antiparallel diode. This does not establish that a particular physical MOSFET was selected or that its switching losses were modeled.

The shown values include an on-resistance of 1e−3 ohms, snubber resistance Rs of 1e5 ohms and snubber capacitance Cs set to inf. Rs is resistance; Cs is capacitance. Calling Cs an infinite off-state resistance mixes two different parameters.

In the relevant legacy series-RC snubber convention, infinite capacitance leaves a resistive snubber path. It is not the same as removing the snubber by making its resistance infinite. Always read the documentation for the exact block and software release, because similarly named modern blocks can use different parameterizations.

A MOSFET or IGBT is also not normally a latching thyristor that stays on until manually stopped. Its gate-drive behavior and current paths depend on the device type. Ideal switch models omit many physical effects, including detailed gate charge, recovery, switching energy and temperature dependence.

The Specialized Power Systems library was removed in R2026a. MathWorks provides migration guidance for Simscape Electrical blocks. Preserve a copy of the original model before conversion, review unsupported or partially converted blocks, and compare the converted model's behavior under the same documented conditions.

Create Three Phase References

For a balanced positive-sequence reference set, define v_a* = V_pksin(ωt), v_b* = V_pksin(ωt − 2π/3), and v_c* = V_pksin(ωt + 2π/3). The fundamental references are separated by 120 electrical degrees.

The same source voltage and intended control law should be used consistently across phases unless the experiment deliberately studies imbalance. Copying one phase subsystem is convenient, but check its reference shift and measurement polarity after duplication.

Several modulation methods can control a CHB. Nearest-level control chooses a voltage step close to the reference. Carrier-based PWM varies the time spent in neighboring states. Selective harmonic elimination chooses switching angles to satisfy specified harmonic equations. These methods should not be described as interchangeable pulse generators.

Published work on CHB phase-shifted and phase-disposition modulation illustrates how the modulation choice affects waveform quality and cell use. For this introductory article, we will use an ideal nearest-level construction because its level arithmetic is easy to inspect.

An Ideal MATLAB Waveform Example

The following code generates desired phase-string levels without simulating semiconductor switches. It is a useful reference for checking a more detailed Simulink model. The selected modulation depth is 0.95 and each cell is represented by an ideal 24 V step.

f0 = 50;
fs = 100000;
cells = 5;
Vdc = 24;
ma = 0.95;
t = (0:round(fs/f0)-1)'/fs;
theta = 2*pi*f0*t;
phaseShift = [0,-2*pi/3,2*pi/3];
reference = ma*cells*sin(theta+phaseShift);
level = round(reference);
level = min(cells,max(-cells,level));
vPhase = Vdc*level;
vAB = vPhase(:,1)-vPhase(:,2);
vBC = vPhase(:,2)-vPhase(:,3);
vCA = vPhase(:,3)-vPhase(:,1);

subplot(2,1,1);
stairs(t,vPhase);
ylabel('String voltage (V)');
legend('A','B','C'); grid on;
subplot(2,1,2);
stairs(t,[vAB,vBC,vCA]);
ylabel('Line voltage (V)'); xlabel('Time (s)');
legend('AB','BC','CA'); grid on;
disp('Available levels visited by phase A:');
disp(unique(vPhase(:,1))');

The code rounds a normalized reference to the nearest available integer level and multiplies it by the cell voltage. It does not generate sixty safe gate signals, balance fifteen sources or model a motor. No fresh MATLAB execution is claimed; run it in your installation to inspect the resulting steps.

To allocate a requested level of +3, one simple ideal assignment inserts three cells at +Vdc and leaves two at zero. A level of −2 inserts two negative cells and three zero cells. Several cell combinations can produce the same total voltage, which introduces a useful control choice.

Always using the same first cells can distribute losses and source energy unevenly. A practical controller may rotate assignments or use source-voltage information to select cells. The total voltage command is therefore only the first stage of a complete modulation algorithm.

Distinguish Phase and Line Voltages

A line voltage is a difference between two phase terminals: v_AB = v_A − v_B. The three line voltages satisfy v_AB + v_BC + v_CA = 0 at each instant when defined consistently. This is a useful wiring and sign check.

The term phase voltage needs a reference. A phase-string voltage may be measured relative to a converter star point. A load phase voltage may instead be measured relative to a floating load neutral. Those references are not automatically identical, especially when common-mode voltage is present.

The historical phase-voltage plot is retained below. Identify its measurement reference before using its amplitude in a load calculation.

The line-voltage plot shows differences between phase outputs. With five equal cells per phase, subtracting two available phase levels gives a theoretical set of up to twenty-one integer voltage differences. A particular three-phase modulation pattern does not necessarily visit every one of those possible differences.

For balanced sinusoidal fundamentals, line-to-line fundamental RMS is √3 times phase-to-neutral fundamental RMS. This relation should not be applied blindly to the total RMS of arbitrary stepped waveforms. Separate the fundamental from harmonics before using familiar sinusoidal formulas.

Estimate Voltage and Current Requirements

Five 24 V cells provide a maximum phase-string magnitude of 120 V. A sinusoidal reference with modulation depth 0.8 would request a 96 V peak fundamental reference, or about 67.9 V RMS. The corresponding balanced line fundamental reference is about 117.6 V RMS.

These are reference values, not guaranteed measured output values. Nearest-level quantization, PWM implementation, dead time, device drops and unequal source voltages change the actual fundamental. Measure it from a settled waveform rather than treating the reference amplitude as a result.

Every series cell carries the phase current, even though each switch primarily blocks its own local DC-link voltage in the ideal topology. More cells reduce the voltage step per cell; they do not divide the series current among the cells. Device current ratings, cooling and fault-current paths still require attention.

For an RL load, L di/dt + Ri = v. Inductance smooths current relative to the stepped voltage, but it stores energy and creates conduction during switching transitions. Antiparallel diodes and valid zero states are therefore part of the current-path model, not decorative additions to the schematic.

Build and Check the Simulink Model in Stages

1. Start with one cell and a low-energy test load.
2. Verify positive, negative and both zero states with known gate commands.
3. Check that no leg receives overlapping on commands.
4. Connect five independently supplied cells in series and verify voltage addition.
5. Implement the selected cell-assignment and modulation method.
6. Duplicate the phase assembly and apply the appropriate reference shifts.
7. Measure cell voltages, phase-string voltages, line voltages and load currents.
8. Repeat with smaller simulation steps and compare the important results.

Choose a simulation step that resolves switching transitions and control updates. A waveform may look smooth at a coarse step while short pulses are missed. Record the solver, step size, modulation method and source values with every plot.

Separate startup from steady-state analysis. Capacitor initialization, current transients and controller startup can all influence the first few cycles. Use an integer number of settled fundamental periods when calculating a coherent harmonic spectrum.

Review Harmonics, Losses and Source Balance

THD compares the RMS sum of selected higher harmonics with fundamental RMS. State the harmonic range and whether switching-frequency components are included. A finer staircase can improve a waveform, but level count alone does not determine THD, efficiency or electromagnetic interference.

Filtering also requires a design, not just an instruction to add a filter. Load impedance, switching frequency, resonance, damping and allowable voltage drop affect the result. A filter that improves a no-load voltage trace may interact poorly with a changing load.

With ideal fixed sources, cell voltages cannot drift, so the simulation hides DC-link balancing demands. Capacitor-fed or renewable-source cells need energy and voltage control. Check the average power of each cell and the direction of energy flow instead of looking only at the combined AC voltage.

The original Simulink project page remains available for historical context. Its presence does not establish compatibility with a current release or validate the revised switching requirements. For a topology comparison, see the 11-level capacitor-clamped inverter; its capacitor arrangement and balancing problem differ from a conventional CHB.

Introduce One Controlled Nonideality at a Time

After checking equal ideal sources, reduce one cell's DC voltage by a known amount. Its positive and negative steps should change accordingly, and formerly equivalent cell assignments may no longer produce identical total voltages. This demonstrates why a controller needs the actual cell voltages when accurate output tracking matters.

Next, investigate a disabled cell in a deliberately defined bypass model. Reducing the available cells changes voltage capability and the available level set. A physical failed semiconductor cannot simply be assumed to become a harmless zero-voltage source; the bypass path and fault isolation must be explicitly designed.

Finally, add realistic switch conduction drops and switching delays using appropriate device models. Compare the voltage error, current distortion and estimated losses with the ideal case. Keeping these experiments separate makes it possible to identify which assumption caused each change, instead of attributing every unexpected waveform to the modulation algorithm.

Frequently Asked Questions

How many DC links are needed?

A conventional symmetric eleven-level three-phase CHB has five cells per phase, giving fifteen local DC links. Visible pulse inputs are control signals and should not be counted as supplies.

Why do I obtain only six phase levels?

One possible cause is allowing only positive and negative states in each of five equal cells. Include correctly controlled zero states and inspect the summed voltage.

Does a multilevel output automatically have low distortion?

No. Source balance, modulation, switching timing and the measurement bandwidth all matter. Report a calculated spectrum under stated conditions.

Can all the DC-source negatives be connected together?

Not in the conventional isolated-cell arrangement described here. The cell sources must preserve the intended electrical separation.

Does the ideal MATLAB example produce gate pulses?

No. It produces reference voltage levels. Safe switch sequencing, dead time and current-path handling require a separate implementation.