11-Level 3-Phase Capacitor Clamped Inverter

Hello friends! Today we will study an 11-level, three-phase capacitor-clamped inverter in MATLAB and Simulink. We will move from the meaning of a voltage level to the phase-leg circuit, switching signals, capacitor voltages and output measurements.

The project uses the flying-capacitor approach. Its intermediate voltage levels depend on stored capacitor voltages and the selected switching states. The capacitors do not create energy or automatically turn a low-voltage source into an unlimited high-voltage supply.

This tutorial explains the historical simulation and provides a structured way to examine or rebuild it. The retained screenshots show the original model; the numerical examples below illustrate design calculations and are not claimed as newly measured results from that model.

What Does an 11-Level Inverter Mean?

An inverter converts DC power into an alternating output by switching the connections between its source, energy-storage elements and load. “Eleven levels” describes the distinct voltage values available at a specified output measurement point. It does not mean eleven phases or eleven separate AC frequencies.

Consider an ideal, balanced 11-level phase leg with total DC-link voltage Vdc. Relative to the negative DC rail, its possible pole voltages can be written as 0, Vdc/10, 2Vdc/10 and so on up to Vdc. Relative to the DC midpoint, these same levels are shifted by −Vdc/2.

For an illustrative 600 V DC link, the step size is 600/10 = 60 V. The centered levels are −300, −240, −180, −120, −60, 0, 60, 120, 180, 240 and 300 V. This example specifies a mathematical voltage scale, not the voltage used in the original project file.

A modulation scheme selects these available levels over time to produce a desired fundamental component. The instantaneous waveform remains switched. An increased number of levels can improve the voltage approximation, but does not remove every harmonic or eliminate the need to examine the load current.

Read the Overall Simulink Model

The overview contains three phase subsystems, ten control inputs per subsystem, voltage-measurement blocks and separate scopes for phase and line voltages. The 30 incoming signals are control signals. They are not 30 DC power supplies.

A Simulink signal line carries a numerical command or measurement in the model. An electrical connection belongs to the simulated power circuit. Keeping those two kinds of connection separate prevents a common mistake: interpreting a pulse-generator output as an energy source.

The three phase legs share the task of producing an AC set with a defined phase sequence. Their modulation references must be coordinated. Simply copying a phase leg three times without changing its reference phase produces three identical outputs, which gives zero line-to-line voltage in the ideal case.

Inside the Flying-Capacitor Phase Leg

The retained phase-leg drawing shows a stack of twenty MOSFET switch blocks, nested capacitor connections and a DC supply arrangement. The output is taken from the central switching node. The capacitors connect between internal nodes rather than all being connected directly across the source.

In a conventional m-level flying-capacitor leg, there are 2(m − 1) active switches. For m = 11, that gives twenty switches per leg and sixty for three legs. The actual component count also depends on how capacitor stacks are implemented and on the voltage rating assigned to each physical capacitor.

The familiar count of (m − 1)(m − 2)/2 gives 45 flying-capacitor units per phase for the conventional equal-voltage-rated stack realization. It is not a universal count for every modified or reduced-component topology. Trace the actual schematic before using a topology formula as a bill of materials.

The voltage targets form a hierarchy of increments of the basic step voltage. Do not set every capacitor to Vdc/2. That single target belongs to particular simpler topologies, such as a three-level flying-capacitor cell, and does not describe all capacitor branches in an eleven-level leg.

Likewise, connecting DC sources in parallel does not add their voltages. Series connections can add voltage when the sources and grounding arrangement permit it. The source wiring in a simulation must represent the intended electrical arrangement, not just display the desired number next to a block.

Capacitor Voltage Balance Is Part of the Control

A capacitor's voltage changes according to i = C × dv/dt. Over a short interval with approximately constant current, ΔV ≈ I × Δt / C. This is the useful starting point for estimating switching ripple.

Suppose a capacitor carries 2 A for 25 microseconds and we allow a 1 V change during that interval. The simplified capacitance requirement is 2 × 25 microseconds / 1 V = 50 microfarads. The final choice must account for the actual sequence of current paths, ripple-current rating, ESR, voltage rating and balancing behavior.

Different switching combinations can produce the same output level while charging or discharging particular capacitors differently. Those redundant states are valuable because the controller can select among them to influence balance without necessarily changing the requested pole voltage.

That choice depends on current direction. A state that charges a capacitor for one load-current direction can discharge it for the opposite direction. A balancing rule based only on voltage error, with no attention to current paths, can therefore act in the wrong direction.

The Vincotech flying-capacitor reference design illustrates the importance of maintaining the intended capacitor voltage in a simpler three-level converter. The larger project requires the same discipline across more internal voltage targets.

Initial Voltage Is Not Proof of Balancing

Setting every capacitor to its ideal initial voltage can make the first few cycles look correct even if the modulation does not maintain those values. Plot capacitor voltages over a longer interval and apply a small initial imbalance. Observe whether the errors converge, remain bounded or increase.

Also repeat the examination at different load currents and power factors. A capacitor-balancing mechanism that works for one resistive operating point may behave differently with an inductive load or during regeneration.

Stored energy is E = 0.5CV². A 100-microfarad capacitor at 60 V stores 0.18 J. Several capacitor branches can store significant energy collectively. In a physical converter, precharge and discharge arrangements are part of the design; assigning an initial condition in software does not implement them.

Understand the Gate-Signal Network

This image shows the logic that distributes the ten incoming commands and their inverted counterparts to the twenty switch controls. It is a control-routing diagram, rather than a close-up of a transistor's internal construction.

A MOSFET is controlled by gate-to-source voltage. It does not have a base, and it does not behave like an ordinary latching thyristor. In hardware, switching it off means removing the appropriate gate charge through a driver so the gate-to-source voltage falls to the intended off level.

A NOT block supplies a logical complement, but does not provide dead time. Real complementary devices must not conduct simultaneously in a path that shorts a source or capacitor. Gate-driver delay, turn-off behavior and current commutation all affect the required transition design.

Begin by labeling every switch and its intended complementary partner. Do not infer pairing only from vertical adjacency in the drawing. The nested capacitor connections determine which combinations are permitted and which would short charged elements.

Construct the Three-Phase References

A balanced reference set can be expressed as:

va* = Vm sin(ωt)

vb* = Vm sin(ωt − 2π/3)

vc* = Vm sin(ωt + 2π/3)

Here ω = 2πf, and the selected sign convention defines the phase sequence. At 50 Hz, one period is 20 ms and a 120-degree displacement corresponds to 6.667 ms. At 60 Hz, the period is 16.667 ms and the corresponding displacement is about 5.556 ms.

Carrier-based modulation is one possible implementation, but the screenshots do not expose every pulse-generator setting or prove a particular balancing algorithm. Inspect the source blocks and internal logic before assigning a named PWM method to the historical model.

Measure Phase and Line Voltages Correctly

A voltage measurement always has two terminals. Pole voltage relative to the DC midpoint, phase voltage relative to a load neutral and phase voltage relative to an arbitrary simulation reference are not automatically identical.

For a balanced three-wire load with a floating star point, the neutral potential can differ from the DC midpoint because of common-mode voltage. Do not connect that neutral to ground simply to make a plot look familiar unless that connection belongs to the intended circuit.

The line voltages are:

vAB = vA − vB; vBC = vB − vC; vCA = vC − vA

The three line voltages should sum to zero algebraically when they refer to the same three nodes and are measured consistently. This provides a useful diagnostic for wiring and subtraction-sign errors.

The historical line-voltage scope shows differences between phase outputs. A line waveform can contain a different set of instantaneous levels from a single pole waveform. Therefore, count and describe levels at a named measurement point instead of using “eleven levels” for every trace in the model.

The phase-voltage plot should be interpreted with its reference node stated. Three colored traces indicate three plotted signals, not the number of voltage levels. Zoom into a fundamental cycle and inspect the distinct plateaus as well as their timing.

For balanced sinusoidal fundamental components, line RMS voltage is √3 times phase-to-neutral RMS voltage. If the phase fundamental is 230 V RMS, the line fundamental is about 398 V RMS. Do not apply that ratio indiscriminately to total RMS values of arbitrary switched waveforms.

Set Up the Simulation Deliberately

The screenshots belong to the older Specialized Power Systems environment and include powergui. MathWorks documents the removal of that technology starting with R2026a on its SimPowerSystems migration page. Opening an old model in a newer installation can require conversion to native Simscape Electrical blocks.

Use a compatible archived release for historical reproduction, or treat migration as a separate modeling task. Do not mix electrical ports from different modeling technologies as if they were ordinary Simulink signal ports.

1. Record the MATLAB release, required products and model dependencies.
2. Inspect source values and capacitor initial conditions.
3. Check gate-signal routing and prohibited switching combinations.
4. Define the load and the voltage reference nodes.
5. Select a solver and time step appropriate to the switching events.
6. Run long enough to observe startup and a steady operating interval.
7. Record capacitor voltages, phase currents and both voltage sets.

The overview image displays a 10-microsecond discrete setting. Whether that is adequate depends on the switching frequency and what you want to measure. At 5 kHz, one switching period is 200 microseconds, so a 10-microsecond step gives only twenty steps per switching period.

Compare the results after reducing the step size, and look for convergence in the quantities that matter. A clean-looking scope at one resolution does not establish numerical accuracy. Simulated switch transitions and narrow pulses can be missed or distorted by an unsuitable step size.

Assess Waveform Quality and Power

Use a steady-state interval containing an integer number of fundamental cycles for spectral analysis. Include the selected bandwidth and sampling conditions when reporting results. Startup transients and a partial cycle can distort an FFT even when the electrical model is behaving as intended.

For harmonics included in the analysis, voltage THD is:

THD = √(V2² + V3² + … + Vn²) / V1 × 100%

Use consistent RMS harmonic magnitudes. A lower voltage THD does not automatically imply a particular efficiency, and an inductive load may have relatively smooth current while the applied voltage remains strongly switched.

For three phases, instantaneous output power is vaia + vbib + vcic with consistent voltage references. Average that power over a suitable steady interval. Compare it with average DC input power and modeled losses; multiplying unrelated peak values does not give real power.

Ideal switches can hide conduction and switching losses. A claim of converter efficiency requires suitable device loss models and power accounting. A visually smooth waveform is not evidence of 100% efficiency or harmonic-free operation.

Useful Tests and Common Problems

A useful progression is to verify one phase leg first, then replicate it with coordinated phase references. Change one condition at a time: load resistance, inductance, DC voltage, initial capacitor error or modulation amplitude. Keep the original run settings so you can explain which change caused the observed difference.

Define a Quantitative Balance Check

For each capacitor branch, record its target voltage, average measured voltage and peak-to-peak ripple over the same steady-state interval. A useful normalized error is 100 × (Vaverage − Vtarget) / Vtarget. Calculate it separately for each target; comparing raw errors alone can hide the relative severity of a deviation on a lower-voltage branch.

For example, a branch intended to sit at 60 V but averaging 63 V has a +5% mean error. A 120 V branch with the same 3 V excess has a +2.5% error. Neither percentage is automatically acceptable: the permitted range depends on output quality and the stresses on connected devices.

Keep average error separate from switching ripple. A capacitor can average exactly its target while making large excursions every cycle. Conversely, a nearly flat trace can remain at the wrong voltage. Reporting both quantities makes the balancing result much more informative than a single screenshot of the output staircase.

Project Review and Related Resources

The flying-capacitor topology offers intermediate voltage levels and redundant switching states, but brings a substantial capacitor network and balancing problem. More levels increase control and measurement work as well as potential waveform quality. The best topology depends on voltage, power, switching devices and application requirements.

The historical project listing is retained for readers looking for the original resource. Check its stated files and compatibility before relying on it. Compare the topology with our 11-level cascaded H-bridge project, which arranges its energy sources and switching cells differently.

Frequently Asked Questions

Do the capacitors automatically increase the available power?

No. They store and exchange energy. Average load power must come from the source, with losses included. Capacitor voltage balance is a control requirement.

Are the thirty pulse inputs thirty voltage sources?

No. They are switching commands, ten for each phase subsystem. Electrical energy enters through the DC power circuit.

Does an eleven-level output contain no harmonics?

No. Its harmonic content depends on modulation, balance, switching frequency, load and filtering. Evaluate it using defined measurements.

Can the screenshots serve as a complete hardware design?

No. A physical converter also needs gate drivers, isolation, precharge, protection, thermal design and verified component ratings. This article develops understanding of the simulation model.